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参数资料
| 型号： | 03X_ADDR |
| 英文描述： | Byte and Half-Word Addressing in the Am29030 and Am29035 Microprocessors |
| 中文描述： | 字节和半的Word Am29030和Am29035寻址微处理器 |
| 文件页数： | 1/2页 |
| 文件大小： | 66K |
| 代理商： | 03X_ADDR |
PID No. 18415B/0
1 of 2
AMD 29K Family
Technical
Bulletin
Byte and Half-Word Addressing
in the Am29030 and Am29035 Microprocessors
EPD Systems Engineering
April 8, 1994
Purpose
This bulletin elaborates on byte and half word
addressing for the Am29030 and Am29035
microprocessors. In addition, it provides a correction
to a table in the Am29030 and Am29035
Microprocessors User’s Manual and Data Sheet.
Affected Parts and Documentation
This bulletin affects the following parts:
Device
Revision
Am29030 microprocessor
All
Am29035 microprocessor
All
This bulletin affects the following documentation:
PID No.
Title
15723C
Am29030 and Am29035 Microprocessors
User’s Manual and Data Sheet
Byte and Half-Word Addressing
All 29K Family processors use big-endian byte
ordering for internal registers. However, the
Am29030 and Am29035 processors can access
external memory using big- or little-endian format.
The Byte Order (BO) bit of the configuration register
sets the endian orientation. Big-endian orientation
(BO=0) places the most significant bit (MSB) of data
at the address “x..x00” and the least significant bit
(LSB) of data at address “x..x11”. Little-endian
orientation (BO=1) places the MSB at “x..x11” and
the LSB at “x..x00”.
Byte Orientation
General
Register
Memory
Location
("x..x00")
Big endian (BO=0)
aa bb cc dd
Little endian (BO=1)
aa bb cc dd
dd cc bb aa
For all external byte and half-word accesses, the
selection of a byte within an external word is
determined by the two LSBs of an address and the
BO bit. The selection of a half-word within an
external word is determined by the next-to-least
significant bit of an address and the BO bit.
Additionally, the Option field in load and store
instructions determine byte, half-word, or word
accesses for the processor. However, for the
EXBYTE, EXHW, EXHWS, INBYTE, and INHW
instructions, the Byte Pointer (BP) field of the ALU
Status Register determines the position of the half-
word within the word. Restated, when these five
instructions are executed, the appropriate value of the
BP field preempts the LSBs of the address to
determine the position of the byte or half-word.
Finally, for all word and half-word accesses, the
Am29030 and Am29035 processors will either ignore
or force alignment in most cases. Thus, half-word
accesses are forced to be aligned to half-word
boundaries. The processor will trap when an
unaligned half-word access is attempted, which
emulates the non-aligned access in trap code. The
processor will perform unaligned byte accesses. (Note
that this assumes the CPS:TU bit is set. If the
CPS:TU bit is clear, data memory alignment is
ignored. This is described in more detail in Section
3.3.7.3 of the user’s manual.)
For big-endian orientation (BO=0), bytes are ordered
within words such that a 00 in the BP field or in the
least-significant address bits selects the high-order
byte of a word; a 11, the low-order byte of a word.
Again, the BP field is only referenced for the
EXBYTE, EXHW, EXHWS, INBYTE, and INHW
instructions.
For little-endian orientation (BO=1), a 00 in the BP
field or in the two least-significant address bits selects
the low-order byte of a word. A value of 11 selects
the high-order byte.
For a half-word access, only the MSB of the BP field
or the next-to-least-significant address bit selects the
appropriate half-word. Since the LSB of the BP field
or the address bits do not determine the half-word
selection, the alignment of half-word data types are
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