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参数资料
| 型号： | 0805J1000102MXRE03 |
| 厂商： | SYFER TECHNOLOGY LTD |
| 元件分类： | 数据传输滤波器 |
| 英文描述： | 2 FUNCTIONS, 100 V, FEED THROUGH CAPACITOR |
| 封装： | EIA STD PACKAGE SIZE 0805 |
| 文件页数： | 3/4页 |
| 文件大小： | 177K |
| 代理商： | 0805J1000102MXRE03 |
X2Y
The Syfer Balanced Line EMI chip has a unique internal architecture
which provides unbeatable EMC performance for dual line data
transmission.
C1
LINE A
LINE B
C1
C2
The Balanced Line EMI chip replaces decoupling capacitors or 3
terminal feedthrough chips on a 1 for 2 basis and provides line to
line (differential mode) decoupling. Fig 2.
The internal structure furnishes a reduced inductance when
compared to that of a conventional capacitor. This is a result of the
novel internal electrode structure which inherently reduces the
inductance by the cancellation effect of opposing currents in close
proximity.
The capacitance line to ground (common mode) is closely matched
due to the symmetry within the design. As the device includes line
to ground capacitance for both lines, any temperature, ageing and
voltage effects will have an equal influence on both lines therefore
maintaining balanced decoupling.
The construction also allows a capacitance between lines as well as
to ground as shown in Fig 3.
INPUT 2
INPUT 1
INPUT 3
INPUT 4
CHIP CAPACITORS
EARTH
TRACKS
INPUT 2
INPUT 1
INPUT 3
INPUT 4
3 TERMINAL CHIPS
EARTH
TRACKS
BALANCED LINE
EMI CHIP
EARTH
TRACKS
INPUT 2
INPUT 1
INPUT 3
INPUT 4
Fig 1
Fig 2
Fig 3
C2, the line to line capacitance, is half the line to ground
capacitance thus providing coupling of high frequency interference
between balanced lines.
Because the part acts as a decoupling device, the current limitations
of a standard 3 terminal chip do not apply. The single line 3
terminal feedthrough chip carries the signal current through the
very thin feedthrough electrodes within the device which have
limited DC resistance and so can cause excessive heating, hence the
maximum permissible current is often limited to around 300 mA for
a 1206 device. The dual line 3 terminal chip is in by-pass across
two lines and so is unaffected by high signal currents.
Table 1 offers a comparison of decoupling devices and
demonstrates how the Balanced Line EMI chip extends the options
for EMC circuit protection.
Component
Advantages
Disadvantages
Applications
●
Requires 1 per line
●
By-pass
Chip capacitor
●
Industry standard
●
High inductance
●
Low frequency
●
Capacitance matching problems
3 terminal
●
Feedthrough
●
Feedthrough
feedthrough
●
Lower Inductance
●
Current limited
●
Unbalanced lines
●
High frequency
●
Very low inductance
●
By-pass
●
Replaces 2 (or 3) components
●
Balanced lines
Balanced line
●
Negates the effects of
●
Not for unbalanced signal lines
●
High frequency
EMI chip
temperature, voltage and ageing
●
DC electric motors
●
Provides both common mode and
differential mode attenuation
Table 1
A typical application for dual line data transmission would see a
board layout using decoupling chip capacitors or 3 terminal
feedthrough chips as shown in Fig 1.
Integrated Passive Components
Balanced Line EMI Chip
FILTSMX2Y.ver2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 0805J1000102MXT | 功能描述:CAP CER 0805 制造商:knowles syfer 系列:* 零件状态:在售 标准包装:3,000 |
| 0805J1000102MXTE01 | 功能描述:电磁干扰滤波器 0805 1000pF 100v X7R 20% 3-Term C Filter RoHS:否 制造商:STMicroelectronics 电容:12 pF 电路类型: 最大直流电流: 最大直流电阻: 电压额定值:6 V 容差: 端接类型:SMD/SMT 工作温度范围:- 30 C to + 85 C 系列:EMIF03 |
| 0805J1000102MXTE03 | 功能描述:CAP CER 1000PF 100V X7R 0805 制造商:knowles syfer 系列:- 包装:带卷（TR） 零件状态:在售 电容:1000pF 容差:±20% 电压 - 额定:100V 温度系数:X7R（2R1） 工作温度:-55°C ~ 125°C 特性:低 ESL 型（X2Y） 等级:- 应用:旁通，去耦 故障率:- 安装类型:表面贴装，MLCC 封装/外壳:0805（2012 公制） 大小/尺寸:0.079" 长 x 0.049" 宽（2.00mm x 1.25mm） 高度 - 安装（最大值）:- 厚度（最大值）:0.045"（1.15mm） 引线间距:- 引线形式:- 标准包装:3,000 |
| 0805J1000103JDR | 功能描述:CAP CER 0805 制造商:knowles syfer 系列:* 零件状态:在售 标准包装:12,000 |
| 0805J1000103JDT | 功能描述:CAP CER 0805 制造商:knowles syfer 系列:* 零件状态:在售 标准包装:3,000 |
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