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参数资料
| 型号： | 101X14W472MV4T |
| 元件分类： | 数据传输滤波器 |
| 英文描述： | 1 FUNCTIONS, 100 V, DATA LINE FILTER |
| 封装： | ROHS COMPLIANT, EIA STD PACKAGE SIZE 0603, 3 PIN |
| 文件页数： | 3/3页 |
| 文件大小： | 441K |
| 代理商： | 101X14W472MV4T |
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www.johanson dielectrics.com
SOLDER PAD RECOMMENDATIONS
0402 (X07)
0603 (X14)
0805 (X15)
1206 (X18)
1210 (X41)
1410 (X44)
1812 (X43)
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
IN
mm
X
0.020
0.51
0.035
0.89
0.050
1.27
0.065
1.65
0.100
2.54
0.100
2.54
0.125
3.18
Y
0.020
0.51
0.025
0.64
0.035
0.89
0.040
1.02
0.040
1.02
0.040
1.02
0.040
1.02
G
0.024
0.61
0.040
1.02
0.050
1.27
0.080
2.03
0.080
2.03
0.100
2.54
0.130
3.30
V
0.015
0.38
0.020
0.51
0.022
0.56
0.040
1.02
0.045
1.14
0.045
1.14
0.045
1.14
U
0.039
0.99
0.060
1.52
0.080
2.03
0.120
3.05
0.160
4.06
0.160
4.06
0.190
4.83
Z
0.064
1.63
0.090
2.29
0.120
3.05
0.160
4.06
0.160
4.06
0.180
4.57
0.210
5.33
Use of solder mask beneath component is not recommended.
V
Z
X
U
V
G
Y
Z
X
U
V
G
Y
X2Y FILTER & DECOUPLING CAPACITORS
OPTIMIZING X2Y PERFORMANCE
X2Y low inductance capacitors deliver excellent performance in EMI/RFI ltering and power delivery bypass / decoupling applica-
tions. Physical and electrical placement on the PCB is critical in achieving best results.
In EMI Filter applications stray inductance should be minimized between signals and the A and B capacitor pads. Use star or daisy
chain routes, rather than “T” to capacitor pads as shown in Figure 1.
For PDN bypass applications Figure 2 compares the X2Y recommended layout against a poor layout. Because of its long extents
from device terminals to vias, and the wide via separation, the poor layout exhibits approximately 200% L1 inductance, and 150% L2
inductance compared to recommended X2Y layouts.
As with any ceramic capacitor, hand soldering is discouraged due to the risk of thermal crack failure. If hand soldering is employed for
lab evaluation, pre-heat the assembly and utilize contact-less soldering methods such as a hot air tool.
Figure 1: EMI Filtering Recommended Layouts
Good Layout
Poor Layout
Figure 2: Decoupling Layout
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