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参数资料
| 型号： | 110H1001-2RD4 |
| 元件分类： | 电源模块 |
| 英文描述： | 1-OUTPUT AC-DC REG PWR SUPPLY MODULE |
| 封装： | 168.50 X 111.20 MM, 38.70 MM HEIGHT, METAL, CASE H02, MODULE |
| 文件页数： | 4/16页 |
| 文件大小： | 358K |
| 代理商： | 110H1001-2RD4 |
Benign Environment
AC-DC Converters <100 W
H-Family
Edition 2/96 - Melcher AG
10 - 73
MELCHER
The Power Partners.
10.3
Formula for threshold level for desired value of
th:
2
Po (th + 0.3 ms) 100
Uti
=
––––––––––––––––––––– +
Ui min2
Ci min η
where as:
Ci min = minimum internal input capacitance [mF], accord-
ing to table below
Po
= output power [W]
h
= efficiency [%]
th
= hold-up time [ms]
Ui min = minimum input voltage [V]
Uti
= threshold level [V]
Remarks:
The threshold level
Uti of option V2 and V3 is adjusted dur-
ing manufacture to a value according to table "Undervol-
tage monitor functions", section "Option D").
A decoupling diode should be connected in series with the
input to avoid the input capacitance discharging through
other loads connected to the same source voltage.
Option V ACFAIL signal (VME)
This option defines an undervoltage monitoring circuit
for the input or the input and main output voltage
(
Uo1 nom = 5.1 V only) equivalent to option D and generates
the ACFAIL signal (V signal) which conforms to the VME
standard. The low state level of the ACFAIL signal is speci-
fied at a sink current of
IV = 48 mA to UV ≤ 0.6 V (open-col-
lector output of a NPN transistor). The pull-up resistor feed-
ing the open-collector output should be placed on the VME
backplane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time
t h of at least 4 ms before the 5.1 V
output drops to 4.875 V when the 5.1 V output is fully
loaded. This hold-up time
th is provided by the internal input
capacitance. Consequently the working input voltage and
the threshold level
U ti should be adequately above the mini-
mum input voltage
Ui min of the converter so that enough
energy is remaining in the input capacitance.
Table 15: Undervoltage monitor functions
V output
Monitoring
Minimum adjustment range
Typical hysteresis
Uh [ % of Ut]
(VME compatible)
Ui
Uo1
of threshold level
Ut
for
Ut min...Ut max
Uti
Uto
Uhi
Uho
V2
yes
no
Ui min...Ui max 1–
3.0...0.5
-
V3
yes
Ui min...Ui max 1
0.95...0.98
Uo1 2
3.0...0.5
"0"
1 Threshold level adjustable by potentiometer (not recommended for mobile applications)
2 Fixed value between 95% and 98% of Uo1 (tracking), output undervoltage monitoring is not a requirement of VME standard
V output (V2, V3):
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1.
UV ≤ 0.6 V (logic low) corre-
sponds to a monitored voltage level (
Ui and/or Uo1) < Ut.
The current
I V through the open collector should not exceed
50 mA. The NPN output is not protected against external
overvoltages.
UV should not exceed 80 V.
Ui, Uo1 status
V output,
UV
Ui or Uo1 < Ut
low, L,
UV ≤ 0.6 V at IV = 50 mA
Ui and Uo1 > Ut + Uh
high, H,
I V
≤ 25 A at UV = 5.1 V
20
23
5
Vo1+
Vo1–
V
UV
IV
N
29
32
Rp
P
Fig. 14
Output configuration of options V2 and V3
voltage(s) exceed(s)
Ut + Uh. The threshold level Ut is ad-
justable by a potentiometer accessible through a hole in the
front cover.
Versions V2 and V3 are available as shown below.
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 5 as soon as one of the monitored voltages drops below
the preselected threshold level
Ut. The return for this signal
is Vo1– (pin 23). The V output recovers when the monitored
Table 14: Factory potentiometer setting of Uti
Types
110H
230H
Unit
Ci min
0.25
0.05
mF
Uti
94
200
V DC
t h
55
ms
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