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参数资料
| 型号： | 12C887 |
| 英文描述： | Test Prod Wire; Conductor Size AWG:18; No. Strands x Strand Size:65 x 36; Jacket Color:Black; Conductor Material:Copper; Jacket Material:Rubber; Leaded Process Compatible:Yes; Number of Conductors:1 RoHS Compliant: Yes |
| 中文描述： | 实时时钟 |
| 文件页数： | 4/19页 |
| 文件大小： | 193K |
| 代理商： | 12C887 |
DS12C887
12 of 19
UPDATE CYCLE
The DS12C887 executes an update cycle once per second regardless of the SET bit in Register B. When
the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm
bytes is frozen and will not update as the time increments. However, the time countdown chain continues
to update the internal copy of the buffer. This feature allows time to maintain accuracy independent of
reading or writing the time, calendar, and alarm buffers and also guarantees that time and calendar
information is consistent. The update cycle also compares each alarm byte with the corresponding time
byte and issues an alarm if a match or if a “don’t care” code is present in all three positions.
There are three methods that can handle access of the real time clock that avoid any possibility of
accessing inconsistent time and calendar data. The first method uses the update-ended interrupt. If
enabled, an interrupt occurs after every up date cycle that indicates that over 999 ms are available to read
valid time and date information. If this interrupt is used, the IRQF bit in Register C should be cleared
before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP) in Register A to determine if the update cycle is in
progress. The UIP bit will pulse once per second. After the UIP bit goes high, the update transfer occurs
244
s later. If a low is read on the UIP bit, the user has at least 244s before the time/calendar data will
be changed. Therefore, the user should avoid interrupt service routines that would cause the time needed
to read valid time/calendar data to exceed 244
s.
The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in
Register A is set high between the setting of the PF bit in Register C (see Figure 3). Periodic interrupts
that occur at a rate of greater than tBUC allow valid time and date information to be reached at each
occurrence of the periodic interrupt. The reads should be complete within 1 ( tPI/2 + tBUC ) to ensure that
data is not read during the update cycle.
UPDATE-ENDED AND PERIODIC INTERRUPT RELATIONSHIP Figure 3
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