- 您现在的位置：买卖IC网 > PDF目录222090 > 1339-2DVGI (INTEGRATED DEVICE TECHNOLOGY INC) 1 TIMER(S), REAL TIME CLOCK, PDSO8 PDF资料下载
参数资料
| 型号： | 1339-2DVGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | 3 MM, ROHS COMPLIANT, MSOP-8 |
| 文件页数： | 3/26页 |
| 文件大小： | 330K |
| 代理商： | 1339-2DVGI |
IDT1339
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
RTC
IDT
REAL-TIME CLOCK WITH SERIAL I2C INTERFACE
11
IDT1339
REV N 060311
The user determines diode and resistor selection according to the maximum current desired for battery or super cap
charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3 V
system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has
been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be
calculated as follows:
IMAX = (3.3 V - diode drop) / R2
(3.3 V - 0.7 V) / 2k
Ω
1.3 mA
As the super cap or battery charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge
current decreases.
I2C Serial Data Bus
The IDT1339 supports the I2C bus protocol. A device that
sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions. The IDT1339 operates as
a slave on the I2C bus. Within the bus specifications, a
standard mode (100 kHz cycle rate) and a fast mode (400
kHz cycle rate) are defined. The IDT1339 works in both
modes. Connections to the bus are made via the open-drain
I/O lines SDA and SCL.
The following bus protocol has been defined (see the “Data
Transfer on I2C Serial Bus” figure):
Data transfer may be initiated only when the bus is not
busy.
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
not limited, and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Timeout: Timeout is where a slave device resets its
interface whenever Clock goes low for longer than the
timeout, which is typically 35mSec. This added logic deals
with slave errors and recovering from those errors. When
timeout occurs, the slave interface should re-initialize itself
and be ready to receive a communication from the master,
but it will expect a Start prior to any new communication.
相关PDF资料 |
PDF描述 |
|---|---|
| 1339-31DCGI8 | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 13715-806-XTD | 300 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 1374610-3 | INTERCONNECTION DEVICE |
| 1376137-1 | POWER CONNECTOR |
| 1380B-8 | BRASS, GOLD FINISH, PCB TERMINAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 1339-2DVGI8 | 功能描述:实时时钟 RTC BASE RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| 13393 | 制造商:Desco Industries Inc 功能描述:BG STSHLD MTL-IN 16''X30'' 100EA |
| 1339-3/4"x60yd | 功能描述:胶带 1339 TAPE 3/4X60YDS BULK 3" PAPER CORE RoHS:否 制造商:3M Electronic Specialty 产品:Tapes 类型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 颜色: 材料:Copper Foil 宽度:1 in x 18 yds |
| 1339-3/4INX60YDS | 制造商:3M Electronic Products Division 功能描述:80008005862 |
| 1339-3/8"x60yd | 功能描述:胶带 TAPE 3/8 INX60YD BULK 3"CORE RoHS:否 制造商:3M Electronic Specialty 产品:Tapes 类型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 颜色: 材料:Copper Foil 宽度:1 in x 18 yds |
发布紧急采购，3分钟左右您将得到回复。