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参数资料
| 型号： | 13715-806-XTD |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 300 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.150 INCH, GREEN, SOIC-16 |
| 文件页数： | 7/19页 |
| 文件大小： | 582K |
| 代理商： | 13715-806-XTD |
FS714x Programmable Phase-Locked Loop Clock Generator
Data Sheet
Table 12: DC Electrical Specifications
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Overall
Supply current, dynamic
IDD
CMOS mode; FXTAL = 15MHz; FVCO =
400MHz; FCLK = 200MHz; does not include
load current
35
mA
Supply current, static
IDDL
SHUT1, SHUT2 bit both “1”
400
700
A
Serial Communication I/O (SDA, SCL)
High-level input voltage
VIH
0.8*VDD
V
Low-level input voltage
VIL
0.2*VDD
V
Hysteresis voltage
Vhys
0.33*VDD
V
Input leakage current
II
SDA, SCL in read condition
-10
+10
A
Low-level output sink current (SDA)
IOL
SDA in acknowledge condition; VSDA = 0.4V
5
14
mA
Address Select Input (ADDR0, ADDR1)
High-level input voltage
VIH
VDD – 1.0
V
Low-level input voltage
VIL
0.8
V
High-level input current (pull-down)
IIH
VADDRx = VDD
30
A
Low-level input current
IIL
VADDRx = 0V
-1
1
A
Reference Frequency Input (REF)
High-level input voltage
VIH
VDD – 1.0
V
Low-level input voltage
VIL
0.8
V
High-level input current
IIH
VREF = VDD
-1
1
A
Low-level input current (pull-down)
IIL
VREF = 0V
-30
A
Sync Control Input (SYNC)
High-level input voltage
VIH
VDD – 1.0
V
Low-level input voltage
VIL
0.8
V
High-level input current
IIH
VREF = VDD
-1
1
A
Low-level input current (pull-down)
IIL
VREF = 0V
-30
A
Crystal Oscillator Input (XIN)
Threshold bias voltage
VTH
VDD/2
V
High-level input current
IIH
VXIN = VDD
40
A
Low-level input current
IIL
VXIN = GND
-40
A
Crystal frequency
FX
Fundamental mode
35
MHz
Recommended crystal load capacitance*
CL(XTAL)
For best matching with internal crystal
oscillator load
16-18
pF
Crystal Oscillator Output (XOUT)
High-level output source current
IOH
VXOUT = 0
-8.5
mA
Low-level output sink current
IOL
VXOUT = VDD
11
mA
PECL Current Program I/O (IPRG)
Low-level input current
IIL
VIPRG = 0V; PECL mode
-10
10
A
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-level output source current
IOH
VO = 2.0V
19
mA
Low-level output sink current
IOL
VO = 0.4V
-35
mA
Clock Outputs, PECL Mode (CLKN, CLKP)
IPRG bias voltage
VIPRG
VIPRG will be clamped to this level when a
resistor is connected from VDD to IPRG
VDD/3
V
IPRG bias current
IIPRG
IIPRG – (VVDD – VIPRG) / RSET
3.5
mA
Sink current to IPRG current ratio
13
Tristate output current
IZ
-10
10
A
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3
σ from typical. Negative currents indicate flows
out of the device.
15
AMI Semiconductor – Dec, 2007 – Rev. 4.0
www.amis.com
Specifications subject to change without notice
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