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参数资料
| 型号： | 1417G5 |
| 英文描述： | NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery |
| 中文描述： | 网络之光公司1417G5和1417H5型的ATM / SONET / SDH的收发器时钟恢复 |
| 文件页数： | 7/12页 |
| 文件大小： | 149K |
| 代理商： | 1417G5 |
4
Agere Systems Inc.
NetLight 1417G5 and 1417H5-Type
Data Sheet
ATM/SONET/SDH Transceivers with Clock Recovery
January 2000
Application Information (continued)
Noise that couples into the receiver through the power
supply pins can also degrade performance. It is recom-
mended that the pi filter, shown in Figure 2, be used for
both the transmitter and receiver power supplies.
Data Clock and Signal Detect Outputs
The data clock and signal detect outputs of the 1417
transceiver are driven by open-emitter NPN transistors,
which have an output impedance of approximately 7
.
Each output can provide approximately 50 mA maxi-
mum current to a 50
load terminated to VCC – 2.0 V.
Due to the high switching speeds of ECL outputs,
transmission line design must be used to interconnect
components. To ensure optimum signal fidelity, both
data outputs (RD+/RD–) and clock outputs (CLK+/
CLK–) should be terminated identically. The signal
lines connecting the data and clock outputs to the next
device should be equal in length and have matched
impedances. Controlled impedance stripline or micros-
trip construction must be used to preserve the quality
of the signal into the next component and to minimize
reflections back into the receiver, which could degrade
its performance. Excessive ringing due to reflections
caused by improperly terminated signal lines makes it
difficult for the component receiving these signals to
decipher the proper logic levels and can cause transi-
tions to occur where none were intended. Also, by min-
imizing high-frequency ringing, possible EMI problems
can be avoided.
The signal-detect output is LVTTL logic. A logic low at
this output indicates that the optical signal into the
receiver has been interrupted or that the light level has
fallen below the minimum signal detect threshold. This
output should not be used as an error rate indicator,
since its switching threshold is determined only by the
magnitude of the incoming optical signal.
Transceiver Processing
When the process plug is placed in the transceiver's
optical port, the transceiver and plug can withstand
normal wave soldering and aqueous spray cleaning
processes. However, the transceiver is not hermetic,
and should not be subjected to immersion in cleaning
solvents. The transceiver case should not be exposed
to temperatures in excess of 125
°C. The transceiver
pins can be wave soldered at 250
°C for up to 10 sec-
onds. The process plug should only be used once.
After removing the process plug from the transceiver, it
must not be used again as a process plug; however, if it
has not been contaminated, it can be reused as a dust
cover.
Transceiver Optical and Electrical Characteristics
Table 2. Transmitter Optical and Electrical Characteristics (TC = –40
°C to +85 °C; VCC = 3.135 V to 3.465 V)
Parameter
Symbol
Min
Max
Unit
Average Optical Output Power (EOL)
PO
–15.0
–8.0
dBm
Optical Wavelength:
STM-1 (4 nm spectral width, maximum)
STM-4 (2.5 nm spectral width, maximum)
λC
1261
1274
1360
1356
nm
Dynamic Extinction Ratio
EXT
8.2
—
dB
Power Supply Current
ICCT
—
150
mA
Input Data Voltage:
Low
High
VIL
VIH
VCC – 1.81
VCC – 1.025
VCC – 1.62
VCC – 0.88
V
Transmit Disable Voltage
VD
VCC – 1.3
VCC
V
Transmit Enable Voltage
VEN
VEE
VEE + 0.8
V
Laser Bias Voltage
VBIAS
00.70
V
Laser Back-facet Monitor Voltage
VBF
0.01
0.20
V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 1417G5(NETLIGHT) | 制造商:AGERE 制造商全称:AGERE 功能描述:ATM/SONET/SDH Transceivers with Clock Recovery |
| 1417G5A | 制造商:AGERE 制造商全称:AGERE 功能描述:NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery |
| 1417H4A | 制造商:AGERE 制造商全称:AGERE 功能描述:NetLight 1417G4A and 1417H4A ATM/SONET/SDH Transceivers |
| 1417H4A(NETLIGHT) | 制造商:AGERE 制造商全称:AGERE 功能描述:ATM/SONET/SDH Transceivers |
| 1417H5 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FIBER OPTIC TRANSCEIVER |
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