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| 型号： | 15CY7C109B-15VC |
| 英文描述： | 128K x 8 Static RAM(221.62 k) |
| 中文描述： | 128K的× 8静态RAM（221.62十一） |
| 文件页数： | 1/12页 |
| 文件大小： | 221K |
| 代理商： | 15CY7C109B-15VC |
128K x 8 Static RAM
CY7C109B
CY7C1009B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05038 Rev. *A
Revised September 13, 2002
009B
Features
High speed
—tAA = 12 ns
Low active power
— 495 mW (max. 12 ns)
Low CMOS standby power
— 55 mW (max.) 4 mW
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE1, CE2, and OE options
Functional Description[1]
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy mem-
ory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip En-
able One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
a
300-mil-wide
SOJ
package.
The
CY7C1009B
and
CY7C109B are functionally equivalent in all other respects.
Note:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
14
15
Logic Block Diagram
Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW
DE
CODER
SE
NSE
A
M
P
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
512 x256 x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
11
A
13
A
12
A
10
CE1
A
16
A
9
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
109B–2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE
A11
A5
17
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
Selection Guide
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Maximum Access Time (ns)
12
15
20
25
35
Maximum Operating Current (mA)
90
80
75
70
60
Maximum CMOS Standby Current (mA)
10
Maximum CMOS Standby Current (mA)
Low Power Version
2
-
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