参数资料
型号: 1894-40KLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 网络接口
英文描述: DATACOM, INTERFACE CIRCUIT, QCC40
封装: 6 X 6 MM, ROHS COMPLIANT, QFN-40
文件页数: 5/52页
文件大小: 459K
代理商: 1894-40KLFT
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT / ICS 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 13
ICS1894-40
REV C 092909
If a crystal is used as the clocking source, connect it to both
the REF_IN (pin 37) and REF_OUT (pin 36) pins of the
ICS1894-40. A pair of bypass capacitors on either side of
the crystal are connected to ground. The crystal is used in
the parallel resonance or anti-resonance mode. The value
of the load caps serve to adjust the final frequency of the
crystal oscillation. Typical applications would use 33pF load
caps. The exact value will be affected by the board routing
capacitance on REF_IN and REF_OUT pins. Smaller load
capacitors raise the frequency of oscillation.
Once the exact value of load capacitance is established it
will be the same for all boards using the same specification
crystal. The best way to measure the crystal frequency is to
measure the frequency of TXCLK (pin 28) using a frequency
counter with a 1 second gate time. Using the buffered output
TXCLK prevents the crystal frequency from being affected
by the measurement. The crystal specification is shown in
the 25MHz Crystal Specification table.
25 MHz Crystal Specification Table
25 MHz Oscillator Specification table
50 MHz Oscillator Specification table
Status Interface
The ICS1894-40 provides five multi-function configuration
pins that report the results of continual link monitoring by
providing signals that are intended for driving LEDs.
Specifications
Symbol Minimum
Typical Maximum
Unit
Fundamental Frequency (tolerance is sum
of freq., temp., stability and aging.)
F0
24.99875 25.00000
25.00125
MHz
Freq. Tolerance
F/f
± 50
ppm
Input Capacitance
Cin
3
pF
Specifications
Symbol Minimum
Typical Maximum
Unit
Output Frequency
F0
24.99875 25.00000
25.00125
MHz
Freq. Stability (including aging)
F/f
± 50
ppm
Duty cycle CMOS level one-half VDD
Tw/T
35
65
%
VIH
2.79
Volts
VIL
0.33
Volts
Period Jitter
Tjitter
500
pS
Input Capacitance
CIN
3
pF
Specifications
Symbol Minimum
Typical Maximum
Unit
Output Frequency
F0
49.9975 50.00000
50.0025
MHz
Freq. Stability (including aging)
F/f
± 50
ppm
Duty cycle CMOS level one-half VDD
Tw/T
35
65
%
VIH
2.79
Volts
VIL
0.33
Volts
Period Jitter
Tjitter
500
pS
Input Capacitance
CIN
3
pF
相关PDF资料
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