参数资料
型号: 24AA00T-I/MNY
厂商: Microchip Technology
文件页数: 3/34页
文件大小: 0K
描述: IC EEPROM SER 128BIT 1.8V 8TDFN
标准包装: 3,300
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 128(16 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 1.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-TDFN(2x3)
包装: 带卷 (TR)
24AA00/24LC00/24C00
TABLE 1-2:
AC CHARACTERISTICS
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Industrial (I):
Automotive (E):
T A = -40°C to +85°C, V CC = 1.8V to 5.5V
T A = -40°C to +125°C, V CC = 4.5V to 5.5V
Parameter
Clock frequency
Symbol
F CLK
Min
Max
100
Units
kHz
Conditions
4.5V ?? Vcc ? 5.5V (E Temp range)
100
400
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
Clock high time
T HIGH
4000
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
4000
600
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
Clock low time
T LOW
4700
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
4700
1300
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
Start condition hold time
T R
T F
T HD : STA
4000
4000
1000
1000
300
300
ns
ns
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
(Note 1)
4.5V ?? Vcc ? 5.5V (E Temp range)
1.8V ?? Vcc ?? 4.5V
600
4.5V ?? Vcc ? 5.5V
Start condition setup time
T SU : STA
4700
4700
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
1.8V ?? Vcc ?? 4.5V
600
4.5V ?? Vcc ? 5.5V
Data input hold time
Data input setup time
T HD : DAT
T SU : DAT
0
250
ns
ns
(Note 2)
4.5V ?? Vcc ? 5.5V (E Temp range)
250
100
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
Stop condition setup time
T SU : STO
4000
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
4000
600
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
Output valid from clock
(Note 2)
T AA
3500
3500
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
1.8V ?? Vcc ?? 4.5V
900
4.5V ?? Vcc ? 5.5V
Bus free time: Time the bus must T BUF
be free before a new transmis-
sion can start
4700
4700
1300
ns
4.5V ?? Vcc ? 5.5V (E Temp range)
1.8V ?? Vcc ?? 4.5V
4.5V ?? Vcc ? 5.5V
Output fall time from V IH
T OF
20+0.1
250
ns
(Note 1) , CB ?? 100 pF
minimum to V IL maximum
CB
Input filter spike suppression
T SP
50
ns
(Notes 1, 3)
(SDA and SCL pins)
Write cycle time
T WC
4
ms
Endurance
1M
cycles
(Note 4)
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be obtained at www.microchip.com.
? 1996-2011 Microchip Technology Inc.
DS21178H-page 3
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