参数资料
| 型号： | 24AA025T-I/MC |
| 厂商： | Microchip Technology |
| 文件页数： | 5/30页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 8DFN |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（2x3） |
| 包装： | 标准包装 |
| 产品目录页面： | 1445 (CN2011-ZH PDF) |
| 其它名称： | 24AA025T-I/MCDKR |
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24AA024/24LC024/24AA025/24LC025
2.0
PIN DESCRIPTIONS
Pin Function Table
Name
A0
A1
A2
V SS
SDA
SCL
WP
V CC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN/TDFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
SOT-23
5
4
—
2
3
1
—
6
Description
Address Pin AO
Address Pin A1
Address Pin A2
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7 to 5.5V Power Supply
2.1
SDA Serial Data
2.5
Noise Protection
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to V CC (typical 10 k Ω for 100 kHz, 2 k Ω for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24AA024/24LC024/24AA025/24LC025 employs a
V CC threshold detector circuit which disables the
internal erase/write logic if the V CC is below 1.5V at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
2.2
SCL Serial Clock
3.0
FUNCTIONAL DESCRIPTION
The SCL input is used to synchronize the data transfer
from and to the device.
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
2.3
A0, A1, A2
is defined as receiver. The bus has to be controlled
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true. For the SOT-23
package only, pin A2 is not connected.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices (four for the SOT-23 package) may be con-
nected to the same bus by using different Chip Select
bit combinations. These inputs must be connected to
either V CC or V SS .
by a master device that generates the Serial Clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
2.4
WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
V CC or V SS . If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
? 2009 Microchip Technology Inc.
DS21210N-page 5
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