参数资料
| 型号： | 24AA02H-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 3/30页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 8SOIC |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
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24AA02H/24LC02BH
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
AC CHARACTERISTICS
Industrial (I): V CC = +1.7V to 5.5V
Automotive (E): V CC = +2.5V to 5.5V
T A = -40°C to +85°C
T A = -40°C to +125°C
Param.
No.
1
Symbol
F CLK
Characteristic
Clock frequency
Min.
—
Max.
100
Units
kHz
Conditions
1.7V ≤ V CC < 2.5V
—
400
2.5V ≤ V CC ≤ 5.5V
2
3
T HIGH
T LOW
Clock high time
Clock low time
4000
600
4700
—
—
—
ns
ns
1.7V ≤ V CC < 2.5V
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V
1300
—
2.5V ≤ V CC ≤ 5.5V
4
T R
SDA and SCL rise time
—
1000
ns
1.7V ≤ V CC < 2.5V
(Note 1)
—
300
2.5V ≤ V CC ≤ 5.5V
5
T F
SDA and SCL fall time
(Note 1)
—
—
1000
300
ns
1.7V ≤ V CC < 2.5V
2.5V ≤ V CC ≤ 5.5V
6
T HD : STA Start condition hold time
4000
—
ns
1.7V ≤ V CC < 2.5V
600
—
2.5V ≤ V CC ≤ 5.5V
7
T SU : STA
Start condition setup time
4700
—
ns
1.7V ≤ V CC < 2.5V
600
—
2.5V ≤ V CC ≤ 5.5V
8
T HD : DAT Data input hold time
0
—
ns
(Note 2)
9
T SU : DAT
Data input setup time
250
—
ns
1.7V ≤ V CC < 2.5V
100
—
2.5V ≤ V CC ≤ 5.5V
10
11
T SU : STO
T SU : WP
Stop condition setup time
WP setup time
4000
600
4000
—
—
—
ns
ns
1.7V ≤ V CC < 2.5V
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V
600
—
2.5V ≤ V CC ≤ 5.5V
12
T HD : WP
WP hold time
4700
—
ns
1.7V ≤ V CC < 2.5V
600
—
2.5V ≤ V CC ≤ 5.5V
13
14
T AA
T BUF
Output valid from clock
(Note 2)
Bus free time: Time the bus
—
—
1300
3500
900
—
ns
ns
1.7V ≤ V CC < 2.5V
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V
must be free before a new
4700
—
2.5V ≤ V CC ≤ 5.5V
transmission can start
16
T SP
Input filter spike suppression
—
50
ns
(Note 1 and Note 3)
(SDA and SCL pins)
17
T WC
Write cycle time (byte or
—
5
ms
—
page)
18
—
Endurance
1M
—
cycles
25°C, V CC = 5.5V, Block mode
(Note 4)
Note 1: Not 100% tested. C B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T I specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be obtained from Microchip’s web site
at www.microchip.com.
? 2008 Microchip Technology Inc.
DS22105A-page 3
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