参数资料
| 型号： | 24AA04T-I/MC |
| 厂商： | Microchip Technology |
| 文件页数： | 3/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 4KBIT 400KHZ 8DFN |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 4K (2 x 256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN（2x3） |
| 包装： | 带卷 (TR) |
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24AA04/24LC04B
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
T A = -40°C to +85°C, V CC = +1.7V to +5.5V
T A = -40°C to +125°C, V CC = +2.5V to +5.5V
Param.
No.
1
2
Sym.
F CLK
T HIGH
Characteristic
Clock frequency
Clock high time
Min.
—
—
600
Typ.
—
—
—
Max.
400
100
—
Units
kHz
ns
Conditions
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA04)
2.5V ≤ V CC ≤ 5.5V
4000
—
—
1.7V ≤ V CC < 2.5V (24AA04)
3
T LOW
Clock low time
1300
—
—
ns
2.5V ≤ V CC ≤ 5.5V
4700
—
—
1.7V ≤ V CC < 2.5V (24AA04)
4
T R
SDA and SCL rise time
(Note 1)
—
—
—
—
300
1000
ns
2.5V ≤ V CC ≤ 5.5V (Note 1)
1.7V ≤ V CC < 2.5V (24AA04)
(Note 1)
5
T F
SDA and SCL fall time
—
—
300
ns
(Note 1)
—
6
T HD : STA
Start condition hold time
600
—
—
ns
2.5V ≤ V CC ≤ 5.5V
4000
—
—
1.7V ≤ V CC < 2.5V (24AA04)
7
T SU : STA
Start condition setup
600
—
—
ns
2.5V ≤ V CC ≤ 5.5V
time
4700
—
—
1.7V ≤ V CC < 2.5V (24AA04)
8
T HD : DAT
Data input hold time
0
—
—
ns
(Note 2)
—
9
T SU : DAT
Data input setup time
100
—
—
ns
2.5V ≤ V CC ≤ 5.5V
250
—
—
1.7V ≤ V CC < 2.5V (24AA04)
10
T SU : STO
Stop condition setup
600
—
—
ns
2.5V ≤ V CC ≤ 5.5V
time
4000
—
—
1.7V ≤ V CC < 2.5V (24AA04)
11
12
T AA
T BUF
Output valid from clock
(Note 2)
Bus free time: Time the
—
—
1300
—
—
—
900
3500
—
ns
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA04)
2.5V ≤ V CC ≤ 5.5V
bus must be free before
4700
—
—
1.7V ≤ V CC < 2.5V (24AA04)
a new transmission can
start
13
T OF
Output fall time from V IH
minimum to V IL
20+0.1C B
—
—
—
250
250
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA04)
maximum
14
T SP
Input filter spike
—
—
50
ns
(Notes 1 and 3)
suppression
(SDA and SCL pins)
15
T WC
Write cycle time
—
—
5
ms
—
(byte or page)
16
—
Endurance
1M
—
—
cycles 25°C, (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a T I specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be obtained from Microchip’s web site
at www.microchip.com.
? 2009 Microchip Technology Inc.
DS21708K-page 3
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