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参数资料
| 型号： | 24AA512-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 7/36页 |
| 文件大小： | 0K |
| 描述： | EEPROM 512KB 1.8V 400KHZ 8TSSOP |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1447 (CN2011-ZH PDF) |
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24AA512/24LC512/24FC512
4.0
BUS CHARACTERISTICS
4.5
Acknowledge
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit. See Figure 4-2 for acknowledge timing.
Note: The 24XX512 does not generate any
Acknowledge bits if an internal programming
cycle is in progress.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
4.1
Bus Not Busy (A)
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX512) will leave the data line high to enable
the master to generate the Stop condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
? 2010 Microchip Technology Inc.
DS21754M-page 7
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| 24AA256T-I/ST | IC EEPROM 256KBIT 400KHZ 8TSSOP |
| 24LC256T-I/MS | IC EEPROM 256KBIT 400KHZ 8MSOP |
| 25LC256-I/ST | IC EEPROM 256KBIT 10MHZ 8TSSOP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24AA512SC-I/S17K | 功能描述:SERIAL EEPROM WAFER 制造商:microchip technology 系列:- 零件状态:在售 存储器类型:非易失 存储器格式:EEPROM 技术:EEPROM 存储容量:512Kb （64K x 8） 时钟频率:400kHz 写周期时间 - 字，页:5ms 访问时间:900ns 存储器接口:I2C 电压 - 电源:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TA） 标准包装:5,000 |
| 24AA512SC-I/S22K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 1.8V SER EE,DIE in WAFFLE PK, 0 DICE WPAC |
| 24AA512SC-I/W17K | 功能描述:SERIAL EEPROM WAFER 制造商:microchip technology 系列:- 零件状态:在售 存储器类型:非易失 存储器格式:EEPROM 技术:EEPROM 存储容量:512Kb （64K x 8） 时钟频率:400kHz 写周期时间 - 字，页:5ms 访问时间:900ns 存储器接口:I2C 电压 - 电源:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TA） 标准包装:5,000 |
| 24AA512SC-I/W22K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 1.8V SER EE,WAFER, 0 WAFER WJAR |
| 24AA512SC-I/WF17K | 功能描述:SERIAL EEPROM WAFER 制造商:microchip technology 系列:- 零件状态:在售 存储器类型:非易失 存储器格式:EEPROM 技术:EEPROM 存储容量:512Kb （64K x 8） 时钟频率:400kHz 写周期时间 - 字，页:5ms 访问时间:900ns 存储器接口:I2C 电压 - 电源:1.7 V ~ 5.5 V 工作温度:-40°C ~ 85°C（TA） 标准包装:5,000 |
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