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参数资料
| 型号： | 24AA65-P |
| 厂商： | Microchip Technology Inc. |
| 英文描述： | 64K 1.8V I 2 C O Smart Serial O EEPROM |
| 中文描述： | 64K的1.8VI 2二氧化碳?串行EEPROM的智能 |
| 文件页数： | 8/12页 |
| 文件大小： | 105K |
| 代理商： | 24AA65-P |
1996 Microchip Technology Inc.
DS21056F-page 5
24AA65
3.6
Device Addressing
A control byte is the rst byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24AA65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most signicant bits of
the word address. The last bit of the control byte denes
the operation to be performed. When set to a one a
read operation is selected, when set to a zero a write
operation is selected. The next two bytes received
dene the address of the rst data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most signicant bit of
the most signicant byte is transferred rst.
Following
the start condition, the 24AA65 monitors the SDA bus
checking the device type identier being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device (24AA65) outputs an
acknowledge signal on the SDA line. Depending upon
the state of the R/W bit, the 24AA65 will select a read
or write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
SLAVE ADDRESS
101
0A2
A1
A0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low is placed onto the bus
by the master transmitter. This indicates to the
addressed slave receiver (24AA65) that a byte with a
word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore
the next byte transmitted by the master is the high-order
byte of the word address and will be written into the
address pointer of the 24AA65. The next byte is the
least signicant address byte. After receiving another
acknowledge signal from the 24AA65 the master device
will transmit the data word to be written into the
addressed memory location. The 24AA65 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24AA65 will not generate acknowledge
signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the rst data
byte are transmitted to the 24AA65 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24AA65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the
receipt of each word, the six lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remain con-
stant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
full, at which time a stop condition should be generated
by the master. If a stop condition is not received, the
cache pointer will roll over to the rst line (byte 0) of the
cache, and any further data received will overwrite pre-
viously captured data. The stop condition can be sent
at any time during the transfer. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin. The 64 byte cache will con-
tinue to capture data until a stop condition occurs or the
operation is aborted (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
S
t
a
r
t
Control
Byte
Word
Address (1)
Word
Address (0)
Data
S
t
o
p
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
Bus Activity
000
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