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参数资料
| 型号： | 24C04A-ESL |
| 厂商： | Microchip Technology Inc. |
| 英文描述： | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 中文描述： | 1K/2K/4K 5.0VI 2二氧化碳串行EEPROM |
| 文件页数： | 7/12页 |
| 文件大小： | 107K |
| 代理商： | 24C04A-ESL |
24C04A
DS11183E-page 4
1998 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is dened as transmitter, and a device
receiving data as receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24C04A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
Up to four 24C04As can be connected to the bus,
selected by A1 and A2 chip address inputs. A0 must
be tied to VCC or VSS.
3.0
BUS CHARACTERISTICS
The following bus protocol has been dened:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
The 24C04A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
(B)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
相关PDF资料 |
PDF描述 |
|---|---|
| 24C04A-ESM | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C04A-ESN | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C04A-IP | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C04A-ISL | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
| 24C04A-ISM | 1K/2K/4K 5.0V I 2 C O Serial EEPROMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 24C04A-ESM | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:4K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C04A-ESN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:4K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C04A-I/J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C04A-I/P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C04A-I/PA41 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:IC-4K CMOS SERIAL EEPROM |
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