参数资料
| 型号： | 24FC256T-I/MF |
| 厂商： | Microchip Technology |
| 文件页数： | 6/38页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256KBIT 1MHZ 8DFN |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256K (32K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN-S（6x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
24AA256/24LC256/24FC256
4.0
BUS CHARACTERISTICS
4.4
Data Valid (D)
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.1
Bus Not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
Each receiving device, when addressed, is obliged to
4.2
Start Data Transfer (B)
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
clock pulse which is associated with this Acknowledge
bit.
commands must be preceded by a Start condition.
Note:
The 24XX256 does not generate any
4.3
Stop Data Transfer (C)
Acknowledge bits if an internal
programming cycle is in progress.
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
DS21203R-page 6
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
? 1998-2011 Microchip Technology Inc.
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