参数资料
| 型号： | 24FC64-I/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 8/44页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 1MHZ 8MSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 产品目录页面： | 1447 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
24AA64/24LC64/24FC64
6.0
WRITE OPERATIONS
6.2
Page Write
6.1
Byte Write
The write control byte, word address and the first data
byte are transmitted to the 24XX64 in the same way as
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the Address Pointer of
the 24XX64. The next byte is the Least Significant
Address Byte. After receiving another Acknowledge
signal from the 24XX64, the master device will transmit
the data word to be written into the addressed memory
location. The 24XX64 acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle and, during this time, the 24XX64
in a byte write. However, instead of generating a Stop
condition, the master transmits up to 31 additional
bytes which are temporarily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 32 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an inter-
nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
will not generate Acknowledge signals (Figure 6-1). If
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command,
but no write cycle will occur, no data will be written and
the device will immediately accept a new command.
After a byte Write command, the internal address coun-
ter will point to the address location following the one
that was just written.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Note:
When doing a write of less than 32 bytes
the data in the rest of the page is refreshed
along with the data bytes being written.
This will force the entire page to endure a
write cycle, for this reason endurance is
specified per page.
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-1FFF) when the pin is tied to V CC . If tied to
V SS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 4-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
DS21189S-page 8
? 1997-2012 Microchip Technology Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| XC6SLX16-N3CSG324C | IC FPGA SPARTAN-6 324CSBGA |
| XC6SLX16-N3CSG225I | IC FPGA SPARTAN-6 225CSBGA |
| 25LC020AT-I/ST | IC EEPROM 2KBIT 10MHZ 8TSSOP |
| 25LC020AT-I/MS | IC EEPROM 2KBIT 10MHZ 8MSOP |
| XC6SLX16-2FT256I | IC FPGA SPARTAN 6 256FTGBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 24FC64T | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:64K I2C? Serial EEPROM |
| 24FC64T-E/CS16K | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:64K I2C? Serial EEPROM |
| 24FC64T-E/MC | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:64K I2C? Serial EEPROM |
| 24FC64T-E/MNY | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:64K I2C? Serial EEPROM |
| 24FC64T-E/MS | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:64K I2C? Serial EEPROM |
发布紧急采购，3分钟左右您将得到回复。