参数资料
| 型号： | 24LC01BT/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 3/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1KBIT 400KHZ 8TSSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1K (128 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
24AA01/24LC01B
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): T A = -40°C to +85°C, V CC = +1.7V to +5.5V
Automotive (E): T A = -40°C to +125°C, V CC = +2.5V to +5.5V
Param.
No.
1
Sym.
F CLK
Characteristic
Clock frequency
Min.
—
Typ.
—
Max.
400
Units
kHz
Conditions
2.5V ≤ V CC ≤ 5.5V
—
—
100
1.7V ≤ V CC < 2.5V (24AA01)
2
T HIGH
Clock high time
600
—
—
ns
2.5V ≤ V CC ≤ 5.5V
4000
—
—
1.7V ≤ V CC < 2.5V (24AA01)
3
4
T LOW
T R
Clock low time
SDA and SCL rise time
1300
4700
—
—
—
—
—
—
300
ns
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA01)
2.5V ≤ V CC ≤ 5.5V
(Note 1)
—
—
1000
1.7V ≤ V CC < 2.5V (24AA01)
5
T F
SDA and SCL fall time
—
—
300
ns
(Note 1)
—
6
7
T HD : STA
T SU : STA
Start condition hold time
Start condition setup
600
4000
600
—
—
—
—
—
—
ns
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA01)
2.5V ≤ V CC ≤ 5.5V
time
4700
—
—
1.7V ≤ V CC < 2.5V (24AA01)
8
T HD : DAT
Data input hold time
0
—
—
ns
(Note 2)
—
9
10
T SU : DAT
T SU : STO
Data input setup time
Stop condition setup
100
250
600
—
—
—
—
—
—
ns
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA01)
2.5V ≤ V CC ≤ 5.5V
time
4000
—
—
1.7V ≤ V CC < 2.5V (24AA01)
11
T AA
Output valid from clock
—
—
900
ns
2.5V ≤ V CC ≤ 5.5V
(Note 2)
—
—
3500
1.7V ≤ V CC < 2.5V (24AA01)
12
T BUF
Bus free-time: Time the
bus must be free before
1300
4700
—
—
—
—
ns
2.5V ≤ V CC ≤ 5.5V
1.7V ≤ V CC < 2.5V (24AA01)
a new transmission can
start
13
T OF
Output fall time from V IH
20+0.1C B
—
250
ns
2.5V ≤ V CC ≤ 5.5V
minimum to V IL
—
—
250
1.7V ≤ V CC < 2.5V (24AA01)
maximum
14
T SP
Input filter spike
—
—
50
ns
(Notes 1 and 3)
suppression
(SDA and SCL pins)
15
T WC
Write cycle time
—
—
5
ms
—
(byte or page)
16
—
Endurance
1M
—
—
cycles 25°C, (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a T I specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be obtained from Microchip’s web site
at www.microchip.com.
? 2009 Microchip Technology Inc.
DS21711J-page 3
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