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参数资料
| 型号： | 24LC128IST |
| 厂商： | Microchip Technology Inc. |
| 元件分类： | EEPROM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS |
| 文件页数： | 12/12页 |
| 文件大小： | 185K |
| 代理商： | 24LC128IST |
1998 Microchip Technology Inc.
DS21191B-page 9
24AA128/24LC128
8.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1
Current Address Read
The 24xx128 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24xx128 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24xx128 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS READ
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, rst the word address must
be set. This is done by sending the word address to the
24xx128 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then, the master issues the
control byte again but with the R/W bit set to a one. The
24xx128 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24xx128 to discontinue transmission
(Figure 8-2). After a random read command, the inter-
nal address counter will point to the address location
following the one that was just read.
8.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24xx128 transmits the
rst data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24xx128 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the nal byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition. To provide sequential reads, the
24xx128 contains an internal address pointer which is
incremented by one at the completion of each opera-
tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 3FFF to address 0000 if the master acknowl-
edges the byte received from the array address 3FFF.
FIGURE 8-2:
RANDOM READ
FIGURE 8-3:
SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
P
S
T
O
P
CONTROL
BYTE
S
T
A
R
T
DATA
A
C
K
N
O
A
C
K
11
00 AA A 1
BYTE
21 0
XX
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
CONTROL
BYTE
DATA
BYTE
S
T
A
R
T
X = Don’t Care Bit
S 1010 AAA 0
210
S 1010 AAA 1
210
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
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