参数资料
型号: 24LC16B-I/MC
厂商: Microchip Technology
文件页数: 3/40页
文件大小: 0K
描述: IC EEPROM 16KBIT 400KHZ 8DFN
标准包装: 150
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 16K (2K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-VFDFN 裸露焊盘
供应商设备封装: 8-DFN(2x3)
包装: 管件
24AA16/24LC16B
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
Automotive (E):
T A = -40°C to +85°C, V CC = +1.7V to +5.5V
T A = -40°C to +125°C, V CC = +2.5V to +5.5V
Param.
No.
1
2
Symbol
F CLK
T HIGH
Characteristic
Clock frequency
Clock high time
Min.
600
Max.
400
100
Units
kHz
ns
Conditions
2.5V ? V CC ? 5.5V
1.7V ? V CC ? 2.5V (24AA16)
2.5V ? V CC ? 5.5V
4000
1.7V ? V CC ? 2.5V (24AA16)
3
T LOW
Clock low time
1300
ns
2.5V ? V CC ? 5.5V
4700
1.7V ? V CC ? 2.5V (24AA16)
4
T R
SDA and SCL rise time
(Note 1)
300
1000
ns
2.5V ? V CC ? 5.5V (Note 1)
1.7V ? V CC ? 2.5V (24AA16)
(Note 1)
5
6
T F
T HD : STA
SDA and SCL fall time
Start condition hold time
600
300
ns
ns
(Note 1)
2.5V ? V CC ? 5.5V
4000
1.7V ? V CC ? 2.5V (24AA16)
7
8
9
10
T SU : STA
T HD : DAT
T SU : DAT
T SU : STO
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
600
4700
0
100
250
600
ns
ns
ns
ns
2.5V ? V CC ? 5.5V
1.7V ? V CC ? 2.5V (24AA16)
(Note 2)
2.5V ? V CC ? 5.5V
1.7V ? V CC ? 2.5V (24AA16)
2.5V ? V CC ? 5.5V
4000
1.7V ? V CC ? 2.5V (24AA16)
11
T AA
Output valid from clock
900
ns
2.5V ? V CC ? 5.5V
(Note 2)
3500
1.7V ? V CC ? 2.5V (24AA16)
12
T BUF
Bus free time: Time the bus
must be free before a new
1300
4700
ns
2.5V ? V CC ? 5.5V
1.7V ? V CC ? 2.5V (24AA16)
transmission can start
13
14
T OF
T SP
Output fall time from V IH
minimum to V IL maximum
Input filter spike suppression ?
20+0.1C B
250
250
50
ns
ns
2.5V ? V CC ? 5.5V
1.7V ? V CC ? 2.5V (24AA16)
(Notes 1 and 3)
(SDA and SCL pins)
15
T WC
Write cycle time ?
5
ms
(byte or page)
16
Endurance
1M
cycles 25°C, (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a T I specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be obtained from Microchip’s web site
at www.microchip.com.
? 2002-2012 Microchip Technology Inc.
DS21703K-page 3
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