参数资料
型号: 24LC16BH-I/P
厂商: Microchip Technology
文件页数: 9/28页
文件大小: 0K
描述: IC EEPROM 16KBIT 400KHZ 8DIP
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 16K (2K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1446 (CN2011-ZH PDF)
24AA16H/24LC16BH
7.0
READ OPERATION
7.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘ 1 ’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, except that once the 24XX16H transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX16H to transmit the next sequentially-
addressed 8-bit word (Figure 7-3).
7.1
Current Address Read
To provide sequential reads, the 24XX16H contains an
The 24XX16H contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘ 1 ’. Therefore, if the previous access
(either a read or write operation) was to address n , the
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
next current address read operation would access data
from address n + 1 . Upon receipt of the slave address
7.4
Noise Protection
with R/W bit set to ‘ 1 ’, the 24XX16H issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer, but does generate a Stop
condition and the 24XX16H discontinues transmission
(Figure 7-1).
The 24XX16H employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
7.2
Random Read
proper device operation, even on a noisy bus.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX16H as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a ‘ 1 ’.
The 24XX16H will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the 24XX16H will discontinue transmis-
sion (Figure 7-2).
FIGURE 7-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
Data (n)
S
T
O
P
SDA Line
S 1 0 1 0 B2 B1 B0 1
P
Bus Activity
? 2008 Microchip Technology Inc.
Block
Select
Bits
A
C
K
N
o
A
C
K
DS22118A-page 9
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