- 您现在的位置：买卖IC网 > PDF目录4417 > 24LC16BHT-I/MNY (Microchip Technology)IC EEPROM 16KBIT 400KHZ 8TDFN PDF资料下载
参数资料
| 型号： | 24LC16BHT-I/MNY |
| 厂商： | Microchip Technology |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 16KBIT 400KHZ 8TDFN |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 16K (2K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN（2x3） |
| 包装： | 标准包装 |
| 产品目录页面： | 1446 (CN2011-ZH PDF) |
| 其它名称： | 24LC16BHT-I/MNYDKR |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
24AA16H/24LC16BH
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24XX16H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16H works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
3.0
BUS CHARACTERISTICS
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
is not busy.
? During data transfer, the data line must remain
3.5
Acknowledge
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
defined (Figure 3-1).
Note:
The 24XX16H does not generate any
Acknowledge bits if an internal program-
3.1
Bus Not Busy (A)
ming cycle is in progress.
Both data and clock lines remain high.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
3.2
Start Data Transfer (B)
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
3.3
Stop Data Transfer (C)
In this case, the slave (24XX16H) will leave the data
line high to enable the master to generate the Stop
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Data
Allowed
Stop
Condition
? 2008 Microchip Technology Inc.
Valid
to Change
DS22118A-page 5
相关PDF资料 |
PDF描述 |
|---|---|
| M1A3PE1500-2FG484 | IC FPGA 1KB FLASH 1.5M 484-FBGA |
| M1A3PE1500-2FGG484 | IC FPGA 1KB FLASH 1.5M 484-FBGA |
| APA450-FG256 | IC FPGA PROASIC+ 450K 256-FBGA |
| ASC36DRYI-S93 | CONN EDGECARD 72POS DIP .100 SLD |
| APA450-FGG256 | IC FPGA PROASIC+ 450K 256-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LC16B-I/MC | 功能描述:电可擦除可编程只读存储器 2kx8 - 2.5V Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LC16B-I/MNY | 功能描述:电可擦除可编程只读存储器 16K 2K X 8 2.5V SERIAL EE IND RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LC16B-I/MS | 功能描述:电可擦除可编程只读存储器 2kx8 - 2.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LC16B-I/MS | 制造商:Microchip Technology Inc 功能描述:Serial EEPROM IC |
| 24LC16B-I/MSG | 功能描述:电可擦除可编程只读存储器 2kx8 - 2.5V Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
发布紧急采购，3分钟左右您将得到回复。