参数资料
型号: 24LC22AT-I/SN
厂商: Microchip Technology
文件页数: 12/24页
文件大小: 0K
描述: IC EEPROM 2KBIT 400KHZ 8SOIC
产品培训模块: I2C Serial EEPROM
标准包装: 3,300
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
其它名称: 24LC22ATI/SN
24LC22A
7.0
READ OPERATION
7.2
Random Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC22A as part of a write operation. After the word
7.1
Current Address Read
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
The 24LC22A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24LC22A
issues an acknowledge and transmits the eight-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC22A
discontinues transmission (Figure 7-1).
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC22A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24LC22A
discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC22A transmits
the first data byte, the master issues an acknowledge
Control
Byte
FIGURE 7-1:
Bus Activity
Master
SDA Line
Bus Activity
CURRENT ADDRESS
READ
S
T
A
R Data n
T
S 10100001
A
C
K
N
O
A
C
K
S
T
O
P
P
as opposed to a Stop condition in a random read. This
directs the 24LC22A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC22A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24LC22A employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 7-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
Word
Address
S
T
A
R
T
Control
Byte
Data n
S
T
O
P
SDA Line
S 1 01 00 00 0
S 1 0 1 0 0 0 0 1
P
Bus Activity
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS21683B-page 12
? 2007 Microchip Technology Inc.
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