参数资料
| 型号： | 24LC65T-I/SM |
| 厂商： | Microchip Technology |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 400KHZ 8SOIC |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 2,100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 6.0 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIJ |
| 包装： | 带卷 (TR) |
24AA65/24LC65/24C65
5.0
READ OPERATION
5.4
Contiguous Addressing Across
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
Multiple Devices
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24XX65's on the same bus.
In this case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14 and A2 as
5.1
Current Address Read
address bit A15.
The 24XX65 contains an address counter that main-
tains the address of the last word accessed, internally
5.5
Noise Protection
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with R/W bit set to one, the
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device
operation even on a noisy bus. All I/O lines incorporate
Schmitt Triggers for 400 kHz (Fast mode) compatibility.
24XX65 issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
5.6
High Endurance Block
the transfer but does generate a Stop condition and the
24XX65 discontinues transmission (Figure 4-3).
The location of the high endurance block within the
memory map is programmed by setting the leading bit
7 (S/HE) of the configuration byte to ‘ 0 ’. The upper bits
5.2
Random Read
of the address loaded in this command will determine
which 4K block within the memory map will be set to
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX65 as part of a write operation (R/W bit set to ‘ 0 ’).
After the word address is sent, the master generates a
Start condition following the acknowledge. This
high endurance. This block will be capable of
10,000,000 erase/write cycles typical (Figure 8-1).
The high endurance block will retain its value as the
high endurance block even if it resides within the
security block range. The high endurance setting
always takes precedence to the security setting.
terminates the write operation, but not before the
internal Address Pointer is set. Then the master issues
the control byte again, but with the R/W bit set to a one.
The 24XX65 will then issue an acknowledge and
transmit the eight-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX65 to discontinue
transmission (Figure 4-4).
5.3
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX65 transmits the
first data byte, the master issues an acknowledge as
opposed to the Stop condition used in a random read.
This acknowledge directs the 24XX65 to transmit the
next sequentially addressed 8-bit word (Figure 4-5).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge, but will
generate a Stop condition.
To provide sequential reads the 24XX65 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
? 2008 Microchip Technology Inc.
Note:
The high endurance block cannot be
changed after the security option has been
set with a length greater than zero. If the
H.E. block is not programmed by the user,
the default location is the highest block of
memory which starts at location 0x1E00
and ends at 0x1FFF.
DS21073K-page 9
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相关代理商/技术参数 |
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| 24LCS21A/P | 功能描述:电可擦除可编程只读存储器 2.5V Dual Mode RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS21A/S | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/SN | 功能描述:电可擦除可编程只读存储器 2.5V Dual Mode RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS21A/W | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPROM WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/WF | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
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