参数资料
型号: 24LCS21A-I/P
厂商: Microchip Technology
文件页数: 13/20页
文件大小: 0K
描述: IC EEPROM 1KBIT 400KHZ 8DIP
产品培训模块: I2C Serial EEPROM
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (128 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
24LCS21A
FIGURE 7-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
Word
Address
S
T
A
R
T
Control
Byte
Data n
S
T
O
P
SDA Line
S 1 0 1 0 0 0 0 0
S 1 0 1 0 0 0 0 1
P
Bus Activity
A
C
K
A
C
K
A
C
K
N
O
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
Bus Activity
Master
Control
Byte
Data n
Data n+1
Data n+2
Data n+X
S
T
O
P
SDA Line
P
Bus Activity
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
7.3
Sequential Read
7.4
Noise Protection
Sequential reads are initiated in the same way as a
random read except that after the 24LCS21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LCS21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LCS21A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
? 2007 Microchip Technology Inc.
The 24LCS21A employs a V CC threshold detector
circuit which disables the internal erase/write logic if the
V CC is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
DS21161H-page 13
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