参数资料
型号: 24LCS21A/P
厂商: Microchip Technology
文件页数: 12/20页
文件大小: 0K
描述: IC EEPROM 1KBIT 400KHZ 8DIP
产品培训模块: I2C Serial EEPROM
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (128 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
24LCS21A
6.0
WRITE PROTECTION
7.0
READ OPERATION
When using the 24LCS21A in the Bidirectional mode,
the VCLK pin can be used as a write-protect control
pin. Setting VCLK high allows normal write operations,
while setting VCLK low prevents writing to any location
in the array. Connecting the VCLK pin to V SS would
allow the 24LCS21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only mode.
Additionally, pin 3 performs a flexible write-protect
function. The 24LCS21A contains a write protection
control fuse whose factory default state is cleared.
Writing any data to address 7Fh (normally the
checksum in D D C applications), sets the fuse which
enables the WP pin. Until this fuse is set, the
24LCS21A is always write enabled (if VCLK = 1 ). After
the fuse is set, the write capability of the 24LCS21A is
determined by both VCLK and WP pins (Table 6-1).
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1 Current Address Read
The 24LCS21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the
24LCS21A issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
TABLE 6-1:
WRITE-PROTECT TRUTH
24LCS21A discontinues transmission (Figure 7-1).
TABLE
FIGURE 7-1:
CURRENT ADDRESS
Control
Byte
VCLK
0
1
1
1
WP
X
X
1/open
0
Address
7Fh Written
X
No
X
Yes
Mode
for
00h-7Fh
Read-only
R/W
R/W
Read-only
Bus Activity
Master
SDA Line
Bus Activity
READ
S
T
A
R
T
S 10100001
A
C
K
Data n
N
O
A
C
K
S
T
O
P
P
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LCS21A as part of a write operation. After the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. Then the master issues the control byte again, but
with the R/W bit set to a one. The 24LCS21A will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24LCS21A
discontinues transmission (Figure 7-2).
DS21161H-page 12
? 2007 Microchip Technology Inc.
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