参数资料
| 型号： | 24LCS22A-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 8SOIC |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
| 其它名称： | 24LCS22A-I/SNG 24LCS22A-I/SNG-ND 24LCS22AI/SN |
24LCS22A
4.0
WRITE OPERATION
4.2
Page Write
4.1
Byte Write
The write control byte, word address and the first data
byte are transmitted to the 24LCS22A in the same way
Following the Start signal from the master, the slave
address (four bits), three zero bits ( 000 ) and the R/W
bit which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24LCS22A.
After receiving another Acknowledge signal from the
24LCS22A the master device will transmit the data
word to be written into the addressed memory location.
The 24LCS22A acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS22A will not
generate Acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
as in a byte write. But instead of generating a Stop
condition the master transmits up to eight data bytes to
the 24LCS22A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the receipt of each word, the three lower order Address
Pointer bits are internally incremented by one. The
higher order five bits of the word address remains
constant. If the master should transmit more than eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 5-2).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
program operation will not halt programming of the
device.
? 2009 Microchip Technology Inc.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
DS21682E-page 9
相关PDF资料 |
PDF描述 |
|---|---|
| 24LCS22AT-I/SN | IC EEPROM 2KBIT 400KHZ 8SOIC |
| XC2S100-5TQ144C | IC FPGA 2.5V 600 CLB'S 144-TQFP |
| 24LC22AT-I/SN | IC EEPROM 2KBIT 400KHZ 8SOIC |
| XC3S400A-4FT256C | IC SPARTAN-3A FPGA 400K 256FTBGA |
| XC3S200A-4FG320C | IC SPARTAN-3A FPGA 200K 320FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LCS22AT-I/SN | 功能描述:电可擦除可编程只读存储器 VESA E-EDID RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS22AT-I/SNG | 功能描述:电可擦除可编程只读存储器 VESA E-EDID Lead Free Package RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS52/P | 功能描述:电可擦除可编程只读存储器 256x8 - 2.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS52/SN | 功能描述:电可擦除可编程只读存储器 256x8 - 2.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS52/ST | 功能描述:电可擦除可编程只读存储器 256x8 - 2.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
发布紧急采购，3分钟左右您将得到回复。