参数资料
| 型号： | 25AA040AT-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 13/34页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 4KBIT 10MHZ 8SOIC |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 4K (512 x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
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25AA040A/25LC040A
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Name
CS
SO
WP
V SS
SI
SCK
HOLD
V CC
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN (1)
1
2
3
4
5
6
7
8
TDFN (1)
1
2
3
4
5
6
7
8
Rotated
TSSOP
3
4
5
6
7
8
1
2
SOT-23
5
4
—
2
3
1
—
6
Function
Chip Select Input
Serial Data Output
Write-Protect Pin
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Note 1:
The exposed pad on the DFN/TDFN packages can be connected to V SS or left floating.
3.1
Chip Select (CS)
3.4
Serial Input (SI)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
3.5
Serial Clock (SCK)
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
The SCK is used to synchronize the communication
between a master and the 25XX040A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
up, a low level on CS is required prior to any sequence
being initiated.
3.6
Hold (HOLD)
3.2
Serial Output (SO)
The HOLD pin is used to suspend transmission to the
25XX040A while in the middle of a serial sequence
The SO pin is used to transfer data out of the
25XX040A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
3.3
Write-Protect (WP)
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS
registers are disabled, but any other operations
function normally. When WP is high, all functions,
including nonvolatile writes, operate normally. At any
time, when WP is low, the write enable reset latch will
be reset and programming will be inhibited. However,
if a write cycle is already in progress, WP going low will
not change or disable the write cycle. See Table 2-4 for
the Write-Protect Functionality Matrix.
? 2003-2011 Microchip Technology Inc.
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX040A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
DS21827G-page 13
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