参数资料
| 型号： | 25AA080BT-I/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT 10MHZ 8MSOP |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (1K x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
25XX080A/B
2.4
Write Enable ( WREN ) and Write
Disable ( WRDI )
The following is a list of conditions under which the
write enable latch will be reset:
The 25XX080A/B contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:
WRITE ENABLE SEQUENCE ( WREN )
CS
?
?
?
?
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
high-impedance
SO
FIGURE 2-5:
WRITE DISABLE SEQUENCE ( WRDI )
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
10
0
high-impedance
SO
? 2007 Microchip Technology Inc.
DS21808D-page 9
相关PDF资料 |
PDF描述 |
|---|---|
| 25AA080AT-I/ST | IC EEPROM 8KBIT 10MHZ 8TSSOP |
| XCV50E-7FG256C | IC FPGA 1.8V C-TEMP 256-FBGA |
| 828347-2 | CONN D-SUB FEM SCREW LOCK KIT |
| XCV50E-6FG256I | IC FPGA 1.8V I-TEMP 256-FBGA |
| XC3S1500-4FGG320I | SPARTAN-3A FPGA 1.5M STD 320FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 25AA080C | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K SPI Bus Serial EEPROM |
| 25AA080C_12 | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K SPI Bus Serial EEPROM |
| 25AA080C-E/MNY | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K SPI Bus Serial EEPROM |
| 25AA080C-E/MS | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K SPI Bus Serial EEPROM |
| 25AA080C-E/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K SPI Bus Serial EEPROM |
发布紧急采购，3分钟左右您将得到回复。