参数资料
型号: 28C17AFT-20/TS
元件分类: PROM
英文描述: 2K X 8 EEPROM 5V, 200 ns, PDSO28
封装: 8 X 20 MM, TSOP-28
文件页数: 1/8页
文件大小: 100K
代理商: 28C17AFT-20/TS
1994 Microchip Technology Inc.
DS11127F-page 1
FEATURES
Fast Read Access Time—150 ns
CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100
A Standby
Fast Byte Write Time—200
s or 1 ms
Data Retention >200 years
High Endurance - Minimum 104 Erase/Write Cycles
Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
Data Polling; Ready/Busy
Chip Clear Operation
Enhanced Data Protection
-VCC Detector
- Pulse Filter
- Write Inhibit
Electronic Signature for Device Identication
5-Volt-Only Operation
Organized 2Kx8 JEDEC Standard Pinout
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package
- 28-Pin Thin Small Outline Package (TSOP)
8x20mm
- 28-Pin Very Small Outline Package (VSOP)
8x13.4mm
Available for Extended Temperature Ranges:
- Commercial: 0C to +70C
- Industrial: -40C to +85C
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM.
The 28C17A
is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy conguration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost exibility in applications.
PACKAGE TYPE
BLOCK DIAGRAM
Pin 1 indicator on PLCC on top of package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
Vcc
WE
NC
A8
A9
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
SS
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
NC
OE
A10
CE
I/O7
I/O6
A7
NC
RDY/BSY
NU
Vcc
WE
NC
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
OE
NC
A9
A8
NC
WE
Vcc
RDY/BSY
NC
A7
A6
A5
A4
A3
A10
CE
I/07
I/06
I/05
I/04
I/03
Vss
I/02
I/01
I/00
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
21
20
19
VSS
I/O2
14
13
12
OE
NC
A9
A8
22
23
24
RDY/BSY
NC
A7
1
2
3
4
5
25
26
27
28
6
7
NC
WE
VCC
A6
A5
A4
A3
I/O7
I/O6
I/O5
I/O4
I/O3
I/O1
I/O0
A0
A1
A2
18
17
16
15
11
10
9
8
DIP/
SOIC
PLCC
TSOP
VSOP
I/O0
I/O7
Input/Output
Buffers
Chip Enable/
Output Enable
Control Logic
CE
OE
Data Protection
Circuitry
A10
Y Gating
16K bit
Cell Matrix
X
Decoder
Y
Decoder
A0
Data
Poll
Auto Erase/Write
Timing
VCC
VSS
WE
L
a
t
c
h
e
s
Program Voltage
Generation
Rdy/
Busy
28C17A
16K (2K x 8) CMOS EEPROM
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