参数资料
| 型号： | 34VL02T/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ SOT23-6 |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.5 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 其它名称： | 34VL02T/OTDKR |
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34VL02
6.0
READ OPERATION
6.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘ 1 ’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, with the exception that after the 34VL02
transmits the first data byte, the master issues acknowl-
edge, as opposed to a Stop condition in a random read.
This directs the 34VL02 to transmit the next sequentially
6.1
Current Address Read
addressed 8-bit word (Figure 6-3).
To provide sequential reads, the 34VL02 contains an
The 34VL02 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘ 1 ’. Therefore, if the previous
access (either a read or write operation) was to
address n , the next current address read operation
would access data from address n+1 . Upon receipt of
the slave address with R/W bit set to ‘ 1 ’, the 34VL02
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 34VL02
discontinues transmission (Figure 6-1).
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
6.4 Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 34VL02 devices on the same bus.
In this case, software can use A0 of the control byte as
6.2
Random Read
address bit A8; A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
Random read operations allow the master to access
across device boundaries.
any memory location in a random manner. To perform
this type of read operation, the word address must first
6.5
Noise Protection and Brown-Out
be set. This is done by sending the word address to the
34VL02 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘ 1 ’. The 34VL02 then issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 34VL02
discontinues transmission (Figure 6-2).
The 34VL02 employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 6-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
Data (n)
S
T
O
P
SDA Line
Bus Activity
DS22079A-page 10
S
A
C
K
P
N
O
A
C
K
? 2008 Microchip Technology Inc.
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