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参数资料
| 型号： | 3512-00 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 3/9页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR 3512 |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 类型： | 预定标器 |
| 频率： | 0Hz ~ 1.5GHz |
| 适用于相关产品： | PE3512 |
| 已供物品： | 板 |
| 其它名称： | 3512-0 3512-0-ND PE3512 EK |
PE3512
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe
pin 1
NC
GND
1
2
6
5
OUT
GND
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
IN
3
4
V DD
Latch-Up Avoidance
SC-70
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Table 5. Pin Descriptions
Pin
No.
1
2
3
4
5
6
Pin
Name
N/C
GND
IN
V DD
GND
OUT
Description
No Connect. This pin should be left open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Input signal pin. DC blocking capacitor
required (100 pF typical).
Power supply pin. Bypassing is required.
Ground pin.
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Device Functional Considerations
The PE3512 divides an input signal, up to a
frequency of 1500 MHz, by a factor of four thereby
producing an output frequency at one-fourth the
input frequency. To work properly with low
impedance, ground referenced interfaces, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
Table 6. Absolute Maximum Ratings
Symbol
V DD
P in
T ST
T OP
V ESD
Parameter/Conditions
Supply voltage
Input Power
Storage temperature
range
Operating temperature
range
ESD voltage (Human
Body Model)
Min
-65
-40
Max
4.0
13
150
85
2000
Units
V
dBm
°C
°C
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Document No. 70-0107-06 │ www.psemi.com
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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