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参数资料
| 型号： | 3D7323K-6 |
| 厂商： | DATA DELAY DEVICES INC |
| 元件分类： | 延迟线 |
| 英文描述： | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP14 |
| 封装： | ROHS COMPLIANT, DIP-14 |
| 文件页数： | 3/4页 |
| 文件大小： | 275K |
| 代理商： | 3D7323K-6 |
3D7323
Doc #06015
DATA DELAY DEVICES, INC.
3
5/10/2006
3 Mt. Prospect Ave. Clifton, NJ 07013
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7323 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 300
PPM/C, which is equivalent to a variation , over
the -40C to 85C operating range, of
±3% from
the room-temperature delay settings and/or
1.0ns, whichever is greater. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to
±1% of the delay settings at
the nominal 5.0VDC power supply and/or 2.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
VDD
-0.3
7.0
V
Input Pin Voltage
VIN
-0.3
VDD+0.3
V
Input Pin Current
IIN
-1.0
1.0
mA
25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Static Supply Current*
IDD
5
mA
High Level Input Voltage
VIH
2.0
V
Low Level Input Voltage
VIL
0.8
V
High Level Input Current
IIH
-1
1
A
VIH = VDD
Low Level Input Current
IIL
-1
1
A
VIL = 0V
High Level Output Current
IOH
-4.0
mA
VDD = 4.75V
VOH = 2.4V
Low Level Output Current
IOL
4.0
mA
VDD = 4.75V
VOL = 0.4V
Output Rise & Fall Time
TR & TF
2
ns
CLD = 5 pf
*IDD(Dynamic) = 3 * CLD * VDD * F
Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/line (pf)
Output Load Capacitance (CLD) = 25 pf max
F = Input frequency (GHz)
相关PDF资料 |
PDF描述 |
|---|---|
| 3D7323K-6000 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323K-8 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-10 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-100 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-1000 | MONOLITHIC TRIPLE FIXED DELAY LINE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 3D7323K-6000 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323K-8 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-10 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-100 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-1000 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
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