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参数资料
| 型号： | 3D7323M-40 |
| 厂商： | DATA DELAY DEVICES INC |
| 元件分类： | 延迟线 |
| 英文描述： | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDIP8 |
| 封装： | ROHS COMPLIANT, DIP-8 |
| 文件页数： | 2/4页 |
| 文件大小： | 275K |
| 代理商： | 3D7323M-40 |
3D7323
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7323 triple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7323 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7323 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
O1
I1
Dela
y
Dela
y
Dela
y
O2
I2
O3
I3
Temp & VDD
Compensatio
VDD
GND
Figure 1: 3D7323 Functional Diagram
Doc #06015
DATA DELAY DEVICES, INC.
2
5/10/2006
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
相关PDF资料 |
PDF描述 |
|---|---|
| 3D7323M-50 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-500 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-6 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-6000 | MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-8 | MONOLITHIC TRIPLE FIXED DELAY LINE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 3D7323M-50 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-500 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-6 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-6000 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
| 3D7323M-8 | 制造商:DATADELAY 制造商全称:Data Delay Devices, Inc. 功能描述:MONOLITHIC TRIPLE FIXED DELAY LINE |
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