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| 型号： | 4210-00 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 3/8页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR 4210 RF SWITCH |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 类型： | 开关，SPDT |
| 频率： | 0Hz ~ 3GHz |
| 适用于相关产品： | PE4210 |
| 已供物品： | 板 |
| 其它名称： | 4210-0 4210-0-ND PE4210 EK |
PE4210
Product Specification
Figure 3. Pin Configuration (Top View)
Pin 1
V DD 1 8 RF1
Exceeding absolute maximum ratings may cause
permanent damage. Functional operation should
be restricted to the limits in the DC Electrical
CTRL
GND
RFC
2
3
4
4210
7
6
5
GND
GND
RF2
Specifications table. Operation between operating
range maximum and absolute maximum for
extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
Table 3. Pin Descriptions
When handling this UltraCMOS? device, observe
the same precautions that you would use with
Pin No.
1
Pin Name
V DD
Description
Nominal 3 V supply connection. A bypass
capacitor (100 pF) to the ground plane
should be placed as close as possible to
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
the pin
2
3
CTRL
GND
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
Ground connection. Traces should be
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
physically short and connected to ground
4
RFC
plane for best performance.
Common RF port for switch 1
Table 5. Control Logic Truth Table
5
6
RF2
GND
RF2 port 1
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFC to RF1
RFC to RF2
7
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Control Logic
The control logic input pin (CTRL) is typically
8 RF1 1 RF1 port
Note 1. All RF pins must be DC blocked with an external series
capacitor or held at 0 V DC .
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V DD . For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
Table 4. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max
Units
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V DD pin when the
control logic input voltage level exceeds V DD .)
V DD
Power Supply Voltage
-0.3
4.0
V
V I
T ST
T OP
Voltage on any input
Storage temperature range
Operating temperature range
-0.3
-65
-40
V DD + 0.3
+150
+85
V
°C
°C
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE4210 in the 8-lead 3 x 3 mm MSOP package is
MSL1.
P IN
V ESD1
Input power (50 ? )
HBM ESD Voltage
200
18
dBm
V
Note: 1. Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
Document No. 70-0037-06 │ www.psemi.com
?2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 8
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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