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| 型号： | 4268-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 3/11页 |
| 文件大小： | 0K |
| 描述： | IC RF SWTICH SP6T 50 OHM 20QFN |
| 标准包装： | 3,000 |
| 系列： | UltraCMOS™ |
| RF 型： | 通用 |
| 频率： | 100MHz ~ 3GHz |
| 特点： | SP6T |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN（4x4） |
| 包装： | 带卷 (TR) |
| 其它名称： | PE4268 |
PE4268
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
TX1
1
15
RX1
Symbol
V DD
V I
Parameter/Conditions
Power supply voltage
Voltage on any input
Min
-0.3
-0.3
Max
4.0
V DD +
0.3
Units
V
V
GND
TX2
GND
GND
2
3
4
5
20-lead QFN
4x4mm
Exposed Solder Pad
14
13
12
11
RX2
GND
RX3
RX4
T ST
T OP
P IN
Storage temperature range
Operating temperature range
TX input power (50 ? )
RX input power (50 ? )
-65
-40
+150
+85
+38
+23
°C
°C
dBm
ESD Voltage (HBM,
MIL_STD 883 Method
3015.7)
1500
V
Table 2. Pin Descriptions
Pin No. Pin Name
Description
V ESD1
ESD Voltage (MM, JEDEC,
JESD22-A114-B)
ESD Voltage (CDM, JEDEC,
JESD22-C101-A)
100
2000
V
V
11
14
1 1
2
3 1
4
5
6
7
8
9
10
1
12 1
13
1
15 1
16
17
18
19 1
20
TX1
GND
TX2
GND
GND
VDD
V3
V2
V1
GND
RX4
RX3
GND
RX2
RX1
GND
GND
GND
ANT
GND
RF I/O - TX1
Ground
RF I/O – TX2
Ground
Ground
Supply
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Ground
RF I/O - RX4
RF I/O - RX3
Ground
RF I/O - RX2
RF I/O - RX1
Ground
Ground
Ground
RF Common – Antenna Input
Ground
Note 1: ANT port rated higher per applications section, see page 4.
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Note 1: Blocking capacitors needed only when connected to an
external non-zero DC voltage.
Table 5. Truth Table
Table 3. DC Electrical Specifications
Path
ANT – RX1
V3
0
V2
0
V1
0
Parameter
V DD Supply Voltage
I DD Power Supply Current
(V DD = 2.6V)
Control Voltage High
Min
2.4
0.7 x V DD
Typ
2.6
13
Max
2.8
20
Units
V
μA
V
ANT – RX2
ANT – RX3
ANT – RX4
ANT - TX1
ANT - TX2
0
0
0
1
1
0
1
1
0
1
1
0
1
x
x
Control Voltage Low
Document No. 70-0165-03 │ www.psemi.com
0.3 x V DD
V
?2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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