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| 型号： | 4302-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 6BIT 50 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 31.5dB |
| 容差： | ±0.15dB |
| 频率范围： | 0 ~ 4GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1012-6 |
PE4302
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
Figure 15. Evaluation Board Layout
Peregrine Specification 101/0112
designed to ease customer evaluation of the
PE4302 Digital Step Attenuator.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of
the internal negative voltage generator is desired,
then connect –VDD (Black banana plug) to
ground. If an external –VDD is desired, then apply
-3V.
J1 should be connected to the parallel port of a
PC with the supplied ribbon cable. The evaluation
software is written to operate the DSA in serial
mode, so Switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the parallel ribbon cable from the evaluation
board. The parallel cable must be removed to
prevent the PC parallel port from biasing the
control pins.
Figure 16. Evaluation Board Schematic
During power up with P/S=1 high and LE=0 or P/
S=0 low and LE=1, the default power-up signal
Peregrine Specification 102/0144
attenuation is set to the value present on the six
control bits on the six parallel data inputs (C0.5 to
C0.5 C1
C2 C4
Vss/GND
C16). This allows any one of the 64 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the
control bits are automatically set to one of four
possible values presented through the PUP
J4
SMA
1
C16
Z=50 Ohm
DATA
10k
10k
CLK
LE
1
2
3
4
5
C16
RFin
DATA
CLK
LE
C8
MLPQ4X4 RFout
PS
U1
GND
15
14
13
12
11
C8
Z=50 Ohm
PS
1
J5
SMA
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6.
Resistor on Pin 1 & 3
A 10 k ? resistor on the inputs to Pin 1 & 3 (Figure
16) will eliminate package resonance between the
VDD
PUP1 PUP2
100 pF
RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Document No. 70-0056-04 │ www.psemi.com
Note: Resistors on pins 1 and 3 are required to avoid package
resonance and meet error specifications over frequency.
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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| 43025-2000 | 功能描述:集管和线壳 RECEPTACLE 20P DUAL ROW RoHS:否 产品种类:1.0MM Rectangular Connectors 产品类型:Headers - Pin Strip 系列:DF50 触点类型:Pin (Male) 节距:1 mm 位置/触点数量:16 排数:1 安装风格:SMD/SMT 安装角:Right 端接类型:Solder 外壳材料:Liquid Crystal Polymer (LCP) 触点材料:Brass 触点电镀:Gold 制造商:Hirose Connector |
| 43025-2000-P | 制造商:Molex 功能描述:Conn Housing F 20 POS 3mm Crimp ST Cable Mount Bag |
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