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参数资料
| 型号： | 4309-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC DSA 6BIT 50 OHM 24-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 31.5dB |
| 容差： | ±0.15dB |
| 频率范围： | 0 ~ 4GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 其它名称： | 1046-1036-6 |
PE4309
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
Figure 5. Evaluation Board Layout
Peregrine Specification 101/0299
designed to ease customer evaluation of the
PE4309 Digital Step Attenuator. Connect J2 by
mini clip to Vdd to power the IC. Connect J8 by
mini clip to power the evaluation board support
circuits. The control bits for the six parallel data
inputs (C0.5 to C16) are controlled using S2-S7 to
select bits or bit combinations. This allows any
attenuation setting to be specified as shown in
Table 6.
The de-embed trace (J6 to J7) estimates the PCB
insertion loss for removal from the evaluation
board measurement data.
To evaluate using customer software, J1 can be
installed using a standard 0.100 IDC header
(some circuit modification required, see
schematic).
The ability to supply different voltages for the
Control circuitry (using J8) and IC Vdd (using J2)
circuits allows for evaluation of circuits using
different control vs. supply voltages.
Figure 6. Evaluation Board Schematic
Peregrine Specification 102/0366
?2007 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0218-07
│ UltraCMOS? RFIC Solutions
Page 4 of 9
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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