参数资料
型号: 49FCT805APYGI
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: FCT SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封装: GREEN, SSOP-20
文件页数: 6/7页
文件大小: 66K
代理商: 49FCT805APYGI
6
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
IDT49FCT805/A
FAST CMOSBUFFER/CLOCKDRIVER
7V
VCC
Pulse
G enerator
D.U.T.
500
RT
VIN
VOUT
50pF
C L
0V
VOH
tPLH
tPHL
VOL
tR
3V
1.5V
tF
2.0V
0.8V
1.5V
OU TPUT
IN PUT
CO NTR O L
INPUT
tPLZ
0V
OU TPU T
NORMALLY
LO W
tPZH
0V
SW ITCH
CLO SED
OU TPU T
NORMALLY
HIGH
EN ABLE
D ISABLE
SW ITCH
O PEN
tPHZ
0V
VOL
VOH
0.3V
1.5V
tPZL
3.5V
3V
1.5V
0V
VOH
tPLH
tPHL
VOL
3V
1.5V
OU TPUT
IN PU T
tSK(p) = tPHL - tPLH
0V
VOH
tPLH1
VOL
1.5V
OUTPU T 1
3V
1.5V
IN PUT
VOH
tSK(o)
VOL
1.5V
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
OUTPUT 2
tPLH1
tSK(o)
tPLH2
tPHL2
0V
VOH
tPLH1
VOL
1.5V
PACKAGE 1
OUTPUT
3V
1.5V
INPU T
VOH
tSK(pp)
VOL
1.5V
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL1
tSK(pp)
tPLH2
tPHL2
PACKAGE 2
OU TPUT
Package Delay
TEST CIRCUITS AND WAVEFORMS
Pulse Skew - tSK(P)
Test Circuits for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test
Switch
Disable LOW
Closed
Enable LOW
Disable HIGH
GND
Enable HIGH
SWITCH POSITION
Enable and Disable Times
Output Skew
Part-to-Part Skew - tSK(PP)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
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