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参数资料
| 型号： | 530CA40M0000BG |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | SMD CRYSTL OSCILLATOR 40MHZ 3.3V |
| 标准包装： | 50 |
| 系列： | Si530 |
| 类型： | XO（标准） |
| 频率： | 40MHz |
| 功能： | 三态（输出启用） |
| 输出： | CMOS |
| 电源电压： | 3.3V |
| 频率稳定性： | ±50ppm |
| 工作温度： | -40°C ~ 85°C |
| 电流 - 电源（最大）： | 88mA |
| 安装类型： | 表面贴装 |
| 尺寸/尺寸： | 0.276" L x 0.197" W（7.00mm x 5.00mm） |
| 高度： | 0.065"（1.65mm） |
| 封装/外壳： | 6-SMD，无引线（DFN，LCC） |
| 包装： | 托盘 |
| 其它名称： | Q3854864 |
S i 5 3 0 / 5 31
R EVISION D
C R YS TA L O SCILLATOR (XO) (10 M H Z T O 1 . 4 GH Z )
Features
?
Available with any-rate output
?
Internal fixed crystal frequency
Si5602
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
ensures high reliability and low
aging
3x better frequency stability than
SAW-based oscillators
?
?
3rd generation DSPLL ? with superior ?
jitter performance
?
?
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Applications
?
Pb-free/RoHS-compliant
Ordering Information:
?
SONET/SDH
?
Test and measurement
?
?
Networking
SD/HD video
?
?
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL ? circuitry
(Top View)
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
NC
1
6
V DD
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
OE
2
5
CLK–
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
GND
3
4
CLK+
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
Si530 (LVDS/LVPECL/CML)
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
OE
1
6
V DD
associated with custom oscillators.
Functional Block Diagram
NC
2
5
NC
V DD
CLK – CLK+
GND
3
4
CLK
Si530 (CMOS)
Any-rate
OE
1
6
V DD
Fixed
10–1400 MHz
Frequency
XO
DSPLL ?
Clock
NC
2
5
CLK–
Synthesis
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.4 5/13
Copyright ? 2013 by Silicon Laboratories
Si530/531
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