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参数资料
| 型号： | 54ACT112DMQB |
| 元件分类： | 锁存器 |
| 英文描述： | ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封装： | CERDIP-16 |
| 文件页数： | 1/8页 |
| 文件大小： | 348K |
| 代理商： | 54ACT112DMQB |
54ACT112
OBSOLETE
July 20, 2009
Dual JK Negative Edge-Triggered Flip-Flop
General Description
The 'ACT112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on S
D or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals
on S
D and CD force both Q and Q HIGH.
Asynchronous Inputs:
LOW input to S
D sets Q to HIGH level
LOW input to C
D sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D and SD makes both Q and Q
HIGH
Features
■ 'ACT112 has TTL-compatible inputs
■ Outputs source/sink 24 mA
■ Standard Microcircuit Drawing (SMD) 5962-8995001
Connection Diagrams
Pin Assigment for
DIP and Flatpack
10097603
Pin Assigment
for LCC
10097605
Pin Descriptions
Pin Names
Description
J
1, J2, K1, K2
Data Inputs
CP
1, CP2
Clock Pulse Inputs
(Active Falling Edge)
C
D1, CD2
Direct Clear Inputs (Active LOW)
S
D1, SD2
Direct Set Inputs (Active LOW)
Q
1, Q2, Q1, Q2
Outputs
FACT is a trademark of Fairchild Semiconductor
2009 National Semiconductor Corporation
100976
www.national.com
100976 Version 2 Revision 2
Print Date/Time: 2009/07/20 16:20:36
54ACT112
Dual
JK
Negative
Edge-Triggered
Flip-Flop
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| 54ACT112DMQB | 制造商:National Semiconductor Corporation 功能描述:Flip Flop JK-Type Neg-Edge 2-Element 16-Pin CDIP Rail 制造商:National Semiconductor 功能描述:Flip Flop JK-Type Neg-Edge 2-Element 16-Pin CDIP Rail |
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