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参数资料
| 型号： | 54ACT715-RD |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CDIP20 |
| 封装： | CERAMIC, DIP-20 |
| 文件页数： | 2/16页 |
| 文件大小： | 323K |
| 代理商： | 54ACT715-RD |
AC Electrical Characteristics
LM1882
54ACT/LM1882
LM1882
V
CC
T
A = +25C
T
A = 55C
T
A = 40C
Symbol
Parameter
(V)
C
L = 50 pF
to +125C
to +85C
Units
C
L = 50 pF
C
L = 50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAXI
Interlaced f
MAX
5.0
170
190
130
150
MHz
(HMAX/2 is ODD)
f
MAX
Non-Interlaced f
MAX
5.0
190
220
145
175
MHz
(HMAX/2 is EVEN)
t
PLH1
Clock to Any Output
5.0
4.0
13.0
15.5
3.5
19.5
3.5
18.5
ns
t
PHL1
t
PLH2
Clock to ODDEVEN
5.0
4.5
15.0
17.0
3.5
22.0
3.5
20.5
ns
t
PHL2
(Scan Mode)
t
PLH3
Load to Outputs
5.0
4.0
11.5
16.0
3.0
20.0
3.0
19.5
ns
AC Operating Requirements
LM1882
54ACT/LM1882
LM1882
Symbol
Parameter
V
CC
T
A = +25C
T
A = 55C
T
A = 40C
Units
(V)
to +125C
to +85C
Typ
Guaranteed Minimums
Control Setup Time
t
sc
ADDR/DATA to LOAD
5.0
3.0
4.0
4.5
ns
t
sc
L/HBYTE to LOAD
3.0
4.0
4.5
ns
Data Setup Time
t
sd
D7–D0 to LOAD+
5.0
2.0
4.0
4.5
ns
Control Hold Time
t
hc
LOAD to ADDR/DATA
5.0
0
1.0
ns
LOAD to L/HBYTE
0
1.0
ns
Data Hold Time
t
hd
LOAD+ to D7–D0
5.0
1.0
2.0
ns
t
rec
LOAD+ to CLK (Note 4)
5.0
5.5
7.0
8.0
ns
Load Pulse Width
t
wld
LOW
5.0
3.0
5.5
ns
t
wld+
HIGH
5.0
3.0
5.0
7.5
ns
t
wclr
CLR Pulse Width HIGH
5.0
5.5
6.5
9.5
ns
t
wck
CLOCK Pulse Width
5.0
2.5
3.0
4.0
3.5
ns
(HIGH or LOW)
Note 4: Removal of Vectored Reset or Restart to Clock.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
7.0
pF
V
CC = 5.0V
C
PD
Power Dissipation
17.0
pF
V
CC = 5.0V
Capacitance
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