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| 型号： | 552AA000108DGR |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, LVPECL OUTPUT |
| 封装： | ROHS COMPLIANT PACKAGE-6 |
| 文件页数： | 1/14页 |
| 文件大小： | 236K |
| 代理商： | 552AA000108DGR |
Rev. 0.6 6/07
Copyright 2007 by Silicon Laboratories
Si552
DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL
OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ
Features
Applications
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL
Clock Synthesis
VDD
CLK+
CLK-
VC
GND
FS
ADC
Ordering Information:
See page 8.
Pin Assignments:
See page 7.
(Top View)
Si5602
1
2
3
6
5
4
VC
GND
FS
VDD
CLK+
CLK–
Si552
REVISION D
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