参数资料
型号: 552AD000104DG
厂商: Silicon Laboratories Inc
文件页数: 1/15页
文件大小: 0K
描述: OSCILL 155.52/156.25MHZ VCXO SMD
标准包装: 25
系列: Si552
类型: VCXO
频率: 155.52MHz
功能: 三态(输出启用)
输出: LVPECL
电源电压: 3.3V
频率稳定性: ±50ppm
工作温度: -40°C ~ 85°C
电流 - 电源(最大): 130mA
安装类型: 表面贴装
尺寸/尺寸: 0.276" L x 0.197" W(7.00mm x 5.00mm)
高度: 0.065"(1.65mm)
封装/外壳: 2820(7150 公制)
包装: 散装
电流 - 电源(禁用)(最大): 75mA
Si 5 52
R EVISION D
D U A L F REQUENCY V OLTAGE - C ON TROLLED C R Y S TA L
O SCILLATOR ( V C X O ) 1 0 MH Z TO 1.4 G H Z
Features
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Available with any-rate output
frequencies from 10–945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL ? with superior
jitter performance
3x better frequency stability than
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Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
Si5602
SAW-based oscillators
Applications
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package and pinout
Pb-free/RoHS-compliant
Ordering Information:
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SONET/SDH
xDSL
10 GbE LAN/WAN
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Low-jitter clock generation
Optical modules
Clock and data recovery
See page 10.
Pin Assignments:
Description
The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced
DSPLL ? circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
See page 9.
(Top View)
and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a
V C
1
6
V DD
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
FS
2
5
CLK–
IC-based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
GND
3
4
CLK+
provides superior supply noise rejection, simplifying the task of generating
low-jitter clocks in noisy environments typically found in communication
systems. The Si552 IC-based VCXO is factory-configurable for a wide
variety of user specifications including frequency, supply voltage, output
format, tuning slope, and temperature stability. Specific configurations are
factory programmed at time of shipment, thereby eliminating the long lead
times associated with custom oscillators.
Functional Block Diagram
V DD
Fixed
Frequency XO
Any-rate
10–1400 MHz
DSPLL ?
CLK- CLK+
Clock Synthesis
ADC
V C
FS
GND
Rev. 1.1 4/13
Copyright ? 2013 by Silicon Laboratories
Si552
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