参数资料
型号: 552CE000118DG
厂商: Silicon Laboratories Inc
文件页数: 2/15页
文件大小: 0K
描述: OSC 3.3V 74.175824MHZ/74.25MHZ
标准包装: 50
系列: Si552
类型: VCXO
频率: 74.1758MHz
功能: 三态(输出启用)
输出: CMOS
电源电压: 3.3V
频率稳定性: ±20ppm
工作温度: -40°C ~ 85°C
电流 - 电源(最大): 98mA
安装类型: 表面贴装
尺寸/尺寸: 0.276" L x 0.197" W(7.00mm x 5.00mm)
高度: 0.065"(1.65mm)
封装/外壳: 6-SMD,无引线(DFN,LCC)
包装: 带卷 (TR)
其它名称: Q3869882
Si5 52
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage 1
Symbol
V DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
Typ
3.3
2.5
1.8
Max
3.63
2.75
1.89
Units
V
V
V
Supply Current
I DD
Output enabled
LVPECL
120
130
CML
LVDS
CMOS
Tristate mode
108
99
90
60
117
108
98
75
mA
mA
Frequency Select
(FS) 2
V IH
V IL
0.75 x V DD
0.5
V
V
Operating Temperature Range
T A
–40
85
oC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.
2. FS pin includes a 17 k ? resistor to VDD.
Table 2. V C Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope
1,2,3
K V
10 to 90% of V DD
33
ppm/V
45
90
135
180
356
Control Voltage Linearity 4
Modulation Bandwidth
V C Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
L VC
BW
Z VC
V CNOM
V C
BSL
Incremental
@ f O
–5
–10
9.3
500
0
±1
±5
10.0
V DD /2
+5
+10
10.7
V DD
%
%
kHz
k ?
V
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.
3. K V variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V C ranging from 10 to 90% of V DD . Incremental slope
determined with V C ranging from 10 to 90% of V DD .
2
Rev. 1.1
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