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参数资料
| 型号： | 554AF000141DG |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | OSCILLATOR VCXO 8-PIN |
| 标准包装： | 25 |
| 系列： | Si554 |
| 类型： | VCXO |
| 频率： | 141MHz |
| 功能： | 三态（输出启用） |
| 输出： | LVPECL |
| 电源电压： | 3.3V |
| 频率稳定性： | ±50ppm |
| 工作温度： | -40°C ~ 85°C |
| 电流 - 电源（最大）： | 130mA |
| 安装类型： | 表面贴装 |
| 尺寸/尺寸： | 0.276" L x 0.197" W（7.00mm x 5.00mm） |
| 高度： | 0.065"（1.65mm） |
| 封装/外壳： | 8-SMD，无引线（QFN，LCC） |
| 包装： | 托盘 |
| 其它名称： | Q5073307 |
Si554
Table 3. CLK± Output Frequency Characteristics
Temperature Stability
Parameter
Nominal Frequency 1,2,3
1,4
Symbol
f O
Test Condition
LVDS/CML/LVPECL
CMOS
T A = –40 to +85 °C
Min
10
10
–20
Typ
—
—
—
Max
945
160
+20
Units
MHz
MHz
–50
–100
—
—
+50
+100
ppm
Absolute Pull Range 1,4
Aging
Power up Time 5
APR
t OSC
Frequency drift over first year.
Frequency drift over 15 year life.
±12
—
—
—
—
—
—
—
±375
±3
±10
10
ppm
ppm
ms
Settling Time After FS[1:0]
t FRQ
Both FS[1] and FS[0] changing
—
—
20
ms
Change
simultaneously
Notes:
1. See Section 3. "Ordering Information" on page 10 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Nominal output frequency set by V CNOM = V DD /2.
4. Selectable parameter specified by part number.
5. Time from power up or tristate mode to f O (to within ±1 ppm of f O ).
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output
Option 1
V O
V OD
V SE
mid-level
swing (diff)
swing (single-ended)
V DD – 1.42
1.1
0.55
—
—
—
V DD – 1.25
1.9
0.95
V
V PP
V PP
LVDS Output
Option 2
V O
V OD
mid-level
swing (diff)
1.125
0.5
1.20
0.7
1.275
0.9
V
V PP
CML Output Option
2
V O
V OD
2.5/3.3 V option mid-level
1.8 V option mid-level
2.5/3.3 V option swing (diff)
1.8 V option swing (diff)
—
—
1.10
0.35
V DD – 1.30
V DD – 0.36
1.50
0.425
—
—
1.90
0.50
V
V
V PP
V PP
CMOS Output Option
3
V OH
V OL
I OH = 32 mA
I OL = 32 mA
0.8 x V DD
—
—
—
V DD
0.4
V
Rise/Fall time (20/80%)
t R, t F
LVPECL/LVDS/CML
CMOS with C L = 15 pF
—
—
—
1
350
—
ps
ns
Symmetry (duty cycle)
SYM
LVPECL:
V DD – 1.3 V
(diff)
LVDS:
1.25 V (diff)
45
—
55
%
Notes:
1. 50 ? to V DD – 2.0 V.
2. R term = 100 ? (differential).
3. C L = 15 pF
CMOS:
V DD /2
Rev. 1.1
3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 554AF000141DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/644.53125MHZ/669.3265MHZ/693.48299MHZ V - Tape and Reel |
| 554AF000145DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/669.32658MHZ/690.5692MHZ/704.38058MHZ V - Trays |
| 554AF000145DGR | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 622.08MHZ/669.32658MHZ/690.5692MHZ/704.38058MHZ V - Tape and Reel |
| 554AF000171DG | 制造商:Silicon Laboratories Inc 功能描述:CNTRLD OSC 531.25MHZ/622.08MHZ/625MHZ/666.51429MHZ VCXO LVPE - Trays |
| 554AF000171DGR | 制造商:Silicon Laboratories Inc 功能描述:CONTROLLED OSCILLATOR 531.25MHZ/622.08MHZ/625MHZ/666.51429MH - Tape and Reel |
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