参数资料
型号: 570EBB000521DG
厂商: Silicon Laboratories Inc
文件页数: 1/32页
文件大小: 0K
描述: OSCILLATOR 512MHZ 2.5V LVPECL
标准包装: 25
系列: Si570
类型: XO(标准)
频率: 512MHz
功能: 三态(输出启用)
输出: LVPECL
电源电压: 2.5V
频率稳定性: ±20ppm
工作温度: -40°C ~ 85°C
电流 - 电源(最大): 130mA
安装类型: 表面贴装
尺寸/尺寸: 0.276" L x 0.197" W(7.00mm x 5.00mm)
高度: 0.065"(1.65mm)
封装/外壳: 8-SMD,无引线(QFN,LCC)
包装: 托盘
其它名称: Q5131156
Si 5 7 0 / S i 5 71
10 MH Z TO 1.4 G H Z I 2 C P ROGRAMMABLE XO/VCXO
Features
?
?
?
?
Any programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I 2 C serial interface
3rd generation DSPLL ? with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
?
?
?
?
?
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
Ordering Information:
?
?
?
SONET/SDH
xDSL
10 GbE LAN/WAN
?
?
?
Low-jitter clock generation
Optical modules
Clock and data recovery
See page 27.
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL ?
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
Pin Assignments:
See page 26.
(Top View)
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I 2 C serial interface. Unlike traditional XO/VCXOs where a different
crystal is required for each output frequency, the Si57x uses one fixed-
NC
1
SDA
7
6
V DD
frequency crystal and a DSPLL clock synthesis IC to provide any-frequency
operation. This IC-based approach allows the crystal resonator to provide
OE
2
5
CLK–
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems.
GND
3
8
4
CLK+
Functional Block Diagram
SCL
Si570
OE
V DD
CLK-
CLK+
SDA
7
Fixed
Frequency
10-1400 MHz
?
DSPLL Clock
V C
1
6
V DD
SDA
XO
Synthesis
SCL
OE
2
5
CLK–
Si571 only
ADC
GND
3
8
4
CLK+
SCL
Rev. 1.4 4/13
V C
GND
Copyright ? 2013 by Silicon Laboratories
Si571
Si570/Si571
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