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参数资料
| 型号： | 5962-8875701EA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 38 MHz, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 13/32页 |
| 文件大小： | 687K |
| 代理商： | 5962-8875701EA |
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20
PLL Conditions with
No Signal at the
SIGIN Input
PC1
VCO adjusts to fo with φDEMOUT = 90
o and V
VCOIN = 1/2 VCC (see Figure 2)
PC2
VCO adjusts to fMIN with φDEMOUT = -360
o and V
VCOIN = 0V (see Figure 4)
PC3
VCO adjusts to fMAX with φDEMOUT = 360
o and V
VCOIN = VCC (see Figure 6)
PLL Frequency
Capture Range
PC1, PC2 or PC3
Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1 or PC3
Yes
PC2
No
Noise Rejection at
Signal Input
PC1
High
PC2 or PC3
Low
AC Ripple Content
when PLL is Locked
PC1
fr = 2fi, large ripple content at φDEMOUT = 90
o
PC2
fr = fi, small ripple content at φDEMOUT = 0
o
PC3
fr = fSIGIN, large ripple content at φDEMOUT = 180
o
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
A small capture range (2fc) is obtained if τ > 2fc ≈ 1/π (2πfL/τ.)
1/2
FIGURE 46. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A)
τ = R3 x C2
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
R3
C2
INPUT
OUTPUT
|F(j
ω)|
ω
-1/
τ
FIGURE 47. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A)
τ1 = R3 x C2;
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
|F(j
ω)|
ω
-1/
τ2
R3
C2
INPUT
OUTPUT
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
-1/
τ3
m
1/
τ3 1/τ2
R4
m =
R4
R3 + R4
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
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相关代理商/技术参数 |
参数描述 |
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| 5962-887590/EA | 制造商:Harris Corporation 功能描述: |
| 5962-8875901EA | 制造商:Texas Instruments 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 16-Pin CDIP Tube 制造商:Texas Instruments 功能描述:FLIP FLOP D-TYPE BUS INTRFC POS-EDGE 3-ST 1-ELEM 16CDIP - Rail/Tube |
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| 5962-8876001PA | 制造商:Texas Instruments 功能描述:OP Amp Dual GP ±22V/44V 8-Pin CDIP Tube 制造商:Texas Instruments 功能描述:OP AMP DUAL GP 22V/44V 8CDIP - Rail/Tube |
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